QUALITY SEMICONDUCTOR, INC
October
1991
Q
1991
DATABOOK
SRAM
FIFO
FCT
QUICKSWITCH™
Quality Semiconductor, Inc.
851 Martin Avenue, Santa Clara, CA 95050-2903
Tel: (408) 450-8080 Fax: (408) 496 0773
©1991 Quality Semiconductor, Inc. All Rights Reserved
QUALITY SEMICONDUCTOR INC.
IMPORTANT NOTICE
Quality Semiconductor, Inc. does not assume any responsibility for use of any product or circuit described
herein, no patent or other licenses are conveyed or implied, and Quality Semiconductor, Inc. reserves the
right, at any time, without notice, to change said circuitry or specifications.
LIFE SUPPORT POLICY
QUALITY SEMICONDUCTOR, INC. PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES FOR SYSTEMS WITHOUT THE EXPRESS WRITTEN
APPROVAL OF THE PRESIDENT OF QUALITY SEMICONDUCTOR, INC. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body , or (b) support or sustain life, and whose failure to perform, when properly used in accordance
with the instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component of a life support device or system is one whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
QSI, QCMOS, and QSFCT are registered trademarks of Quality Semiconductor, Inc.
QuickSwitch and Q are trademarks of Quality Semiconductor, Inc.
Quality Semiconductor, Inc. 851 Martin Avenue, Santa Clara, CA 95050-2903
Tel: (408) 450-8080 Fax: (408) 496 0773.
QUALITY SEMICONDUCTOR INC.
=
■-■ . - -
Static RAM Products 2
FIFO Memory Products 3
FCT-T Logic Products 4
QuickSwitch Products 5
Application Notes 6
Quality And Reliability 7
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
i
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
TABLE OF CONTENTS
GENERAL INFORMATION
Table of contents
Product Selector guide
Product Status Definitions
Numerical product index
Ordering information
Cross reference
STATIC RAM PRODUCT DATA SHEETS
SRAM Ordering Information
SRAM Test Configuration
QS8768
QS8769
QS8780
QS8881/2
QS8883
QS8885/6
QS8888
4Kx4 SRAM in 20 pins
4Kx4 SRAM in 20 pins with fast C3
4Kx4 Cache Tag RAM with Reset
16Kx4 SRAM with Separate I/O
16Kx4 Cache Tag SRAM
16Kx4 SRAM with Output Enable
QS881 80/60
QS88181
QS88182
QS83280
QS83283
QS83285
QS83289
QS83290
QS83291
QS86440
QS86442
QS86444/9
QS86446
QS86447
QS86448
QS812880
8KX18/16 SRAM
8Kx18 Burst Mode SRAM
8Kx18 Cache TAG SRAM
32Kx8 SRAM
32Kx8 SRAM with Fast Address bit
32Kx8 Low Power SRAM
32Kx8 SRAM with Fast Chip Select
32Kx9 SRAM
32Kx9 Burst Mode SRAM
64KX4 SRAM
64Kx4 Cache TAG SRAM
64Kx4 SRAM with Separate I/O
64Kx4 SRAM with Output Enable
64Kx4 SRAM with Address Latch
64Kx4 SRAM 1
Page
1-1
128Kx8 SRAM
2-3
2-4
2-5
2-13
2-21
2-31
2-41
2-51
2-59
2-67
2-77
2-79
2-81
2-89
2-91
2-99
2-101
2-103
2-105
2-113
2-115
2-117
2-125
2-127
2-129
FIFO MEMORY PRODUCT DATA SHEETS
FIFO Ordering Information
FIFO Test Configuration
QS7201/2 512x9 and 1Kx9 FIFO
QS7203/4 2K and 4Kx9 FIFO
QS721 1/2 512x9 and 1Kx9 FIFO with Output Enable
QS7223/4 2Kx9 and 4Kx9 Clocked FIFO
QS7306 64Kx4 Ultra Deep FIFO
QS731 6 64Kx4 Burst Mode Dual Port RAM
3-3
3-4
3-5
3-21
3-39
3-53
3-67
3-69
QUALITY SEMICONDUCTOR INC.
1-1
GENERAL INFORMATION
TABLE OF CONTENTS (Continued)
FCT-T LOGIC PRODUCT DATA SHEETS
FCT-T Ordering Information
FCT-T Test Configuration
29FCT52/3
29FCT520/1
54/74FCT1 38/238
54/74FCT1 39/239
QS54/74FCT1 51/251
QS54/74FCT1 53/253
QS54/74FCT157/8
QS54/74FCT161/3
QS54/74FCT191
QS54/74FCT193
QS54/74FCT240/1/4
QS54/74FCT245/640
QS54/74FCT273
QS54/74FCT280/1280
QS54/74FCT299
QS54/74FCT373
QS54/74FCT374
QS54/74FCT377
QS54/74FCT521
QS54/74FCT540/1
QS54/74FCT543/4
QS54/74FCT573
QS54/74FCT574
QS54/74FCT646/8
QS54/74FCT651/2
QS54/74FCT821/3/5
QS54/74FCT827/8
QS54/74FCT833/53
QS54/74FCT841/3/5
QS54/74FCT861/2/3/4
Registered Transceivers
Pipeline Registers
3- >8 Binary Decoders
Dual 2->4 Binary Decoders
8 Input Multiplexers
Dual 4 Input Multiplexers
Quad 2 Input Multiplexers
4- bit Binary Synchronous Counters
4-bit Binary Up/Down Counters
4-bit Binary Up/Down Counters
8-bit Buffers
8-bit Transceivers
8- bit Register with Clear
9- bit Parity Generator/Checkers
8-bit Universal Shift Register
8-bit Latch
8-bit Register
8-bit Register with Clock Enable
8-bit Identity Comparator
8-bit Buffers
8-bit Latch Transceiver
8-bit Latch
8-bit Register
8-bit Registered Transceiver
8-bit Registered Transceiver
8, 9 and 1 0-bit Registers
10- bit Buffers
Transceivers with Parity
8, 9 and 10-bit Latches
9 and 1 0-bit Transceivers
4-3
4-4
4-27
4-35
4-43
4-49
4-55
4-61
4-67
4-73
4-81
4-89
4-97
4-103
4-109
4-115
4-123
4-129
4-135
4-141
4-147
4-153
4-159
4-167
4-173
4-179
4-187
4-195
4-205
4-211
4-213
4-223
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
TABLE OF CONTENTS (Continued)
FCT2000-T SERIES RESISTOR LOGIC PRODUCT DATA SHEETS
29FCT2052/3
29FCT20520/1
QS54/74FCT2151/251
QS54/74FCT21 53/253
QS54/74FCT215725
QS54/74FCT2161/3
QS54/74FCT2191
QS54/74FCT2193
QS54/74FCT2240/1/4
QS54/74FCT2245/640
QS54/74FCT2273
QS54/74FCT2280/1280
QS54/74FCT2299
QS54/74FCT2373
QS54/74FCT2374
QS54/74FCT2377
QS54/74FCT2521
QS54/74FCT2540/1
QS54/74FCT2543/4
QS54/74FCT2573
QS54/74FCT2574
QS54/74FCT2646/8
QS54/74FCT2651/2
QS54/74FCT2821/3/5
QS54/74FCT2827/8
QS54/74FCT2833/53
QS54/74FCT2841/3/5
QS54/74FCT2861 /2/3/4
Registered Transceivers
Pipeline Registers
8 Input Multiplexers
Dual 4 Input Multiplexers
Quad 2 Input Multiplexers
4-bit Binary Synchronous Counters
4-bit Binary Up/Down Counters
4-bit Binary Up/Down Counters
8-bit Buffers
8-bit Transceivers
8- bit Register with Clear
9- bit Parity Generator/Checkers
8-bit Universal Shift Register
8-bit Latch
8-bit Register
8-bit Register with Clock Enable
8-bit Identity Comparator
8-bit Buffers
8-bit Latch Transceiver
8-bit Latch
8-bit Register
8-bit Registered Transceiver
8-bit Registered Transceiver
8, 9 and 10-bit Registers
10- bit Buffers
Transceivers with Parity
8, 9 and 10-bit Latches
9 and 10-bit Transceivers
Page
4-27
4-35
4-55
4-61
4-67
4-73
4-81
4-89
4-97
4-103
4-109
4-115
4-123
4-129
4-135
4-141
4-147
4-153
4-159
4-167
4-173
-179
-187
-195
-205
-211
4-213
4-223
QUICKSWITCH PRODUCT DATA SHEETS
QuickSwitch Ordering Information
QuickSwitch Test Configuration
QuickSwitch Family Characteristics
QST3383/53 QuickSwitch Bus Exchange
QST3384/54 QuickSwitch Bus Connect
5-3
5-4
5-5
5-17
5-23
QUALITY SEMICONDUCTOR INC.
—
GENERAL INFORMATION
TABLE OF CONTENTS (Continued)
APPLICATION NOTES
AN-01 Ground Bounce Noise in TTL Logic 6-3
AN-02 FIFOs as High Speed Data Queues for Systems 6-21
AN-03 The 6-Transistor SRAM Cell and Its Advantages 6-35
AN -04 High Speed SRAMs and Bus Contention Issues 6-41
AN-05 High Speed SRAMs in Cache and Bit Slice Applications 6-47
AN-06 ZIP Packages for Logic Provide High density and High Speed 6-59
AN-07 Resistor Output Logic Gives High Speed with Low Noise 6-61
AN-08 QSOP Packages Provide High Density in 32-bit Bus Designs 6-63
AN-09 CMOS Bus Switches Provide Zero Delay Bus Communication 6-65
■
QUALITY AND RELIABILITY
PACKAGE INFORMATION
SALES OFFICES
PRODUCT STATUS DEFINITIONS
Data Sheet
Identification
Product
Status
Definition
Advance Information
Preliminary
In Design or
Prototype
(none)
First Production
Full Production
This data sheet contains the key specifications for
product development. The specifications may
change in any manner without notice.
This data sheet contains preliminary data, and
supplementary data may be published at a later date.
QSI reserves the right to make changes to these
specifications at any time without notice in order to improve
the design and supply the best possible product.
This data sheet contains final specifications.
QSI reserves the right to make changes to these
specifications at any time without notice in order to improve
the design and supply the best possible product.
1-4
QUALITY SEMICONDUCTOR INC.
=
GENERAL INFORMATION
SRAM
PRODUCT SELECTOR GUIDE
Part No.
Density
Organization
Fealures
Availability
8768
16K
4Kx4
Common I/O
1Q92
8769
16K
4Kx4
Fast Chip Select
1Q92
8780
16K
4Kx4
Cache Tag
1Q92
88160
128K
8Kx16
Cache Data RAM
2Q92
88180
144K
8Kx18
Cache Data RAM
2Q92
88181
144K
8Kx18
Burst Mode SRAM
2Q92
88182
144K
8Kx18
Cache Tag RAM
2Q92
83280
256K
32Kx8
Common I/O
2Q92
83283
256K
32Kx8
Fast Address bit
2Q92
83285
256K
32Kx8
Low Power
NOW
83289
256K
32Kx8
Fast Chip Select
2Q92
83290
288K
32Kx9
Common I/O
2Q92
83291
288K
32Kx9
Burst Mode
2Q92
86440
256K
64Kx4
Common I/O
2Q92
86442
256K
64Kx4
Cache Tag
2Q92
86444
256K
64Kx4
Separate I/O
2Q92
86446
256K
64Kx4
Output Enable
2Q92
<- O V l\
Address Latch
2Q92
86448
256K
64Kx4
Address Register
2Q92
86449
256K
64Kx4
Separate I/O
2Q92
812880
1024K
128Kx8
Common I/O
4Q92
8881
64 K
16Kx4
Separate I/O
NOW
8882
64K
16Kx4
Separate I/O
NOW
8883
64 K
16Kx4
Cache Tag
NOW
8885
64K
1 6Kx4
Output Enable, 2 CS"
NOW
8886
64 K
16Kx4
Output Enable
NOW
8888
64 K
16Kx4
22-pin, 12 ns
NOW
VV X
FIFO
Part No.
Density
Organization
Features
Availability
7201
4K
512x9
15 ns
NOW
7202
8K
1Kx9
15 ns
NOW
7203
1 6K
2Kx9
15 ns
1Q92
7204
32K
4Kx9
15 ns
1Q92
7211
4K
512x9
15 ns, OE
4Q91
7212
8K
1Kx9
15 ns, OE
4Q91
7223
16K
2Kx9
50Mhz, clocked
1Q92
7229
32K
4Kx9
50Mhz, clocked
1Q92
7306
256K
64Kx4
50Mhz, clocked
2Q92
7316
256K
64Kx4
Burst Mode Dual Port
2Q92
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
FCT Logic
Part No, Part No, Furcfon Bis Insist Availability
240
2240
Buffer
8
X
NOW
241
2241
Buffer
8
NOW
244
2244
Buffer
8
NOW
540
2540
Buffer
8
X
NOW
541
2541
Buffer
8
NOW
827
2827
Buffer
10
NOW
828
2828
Buffer
10
X
NOW
373
2373
Latch
8
NOW
533
2533
Latch
8
X
NOW
841
2841
Latch
10
NOW
843
2843
Latch
9
NOW
845
2845
Latch
8
NOW
273
2273
Register with Clear
8
NOW
374
2374
Register
8
NOW
377
2377
Register with Clock Enable
8
X
NOW
534
2534
Register
8
NOW
821
2821
Register
10
NOW
823
2823
Register
9
NOW
825
2825
Register
8
NOW
29520
292520
Pipeline Registers
8
NOW
29521
292521
Pipeline Registers
8
NOW
245
2245
Transceiver
8
NOW
833
2833
Transceiver w/ Reg. Parity
8
NOW
853
2853
Transceiver with Latched Parity
8
NOW
861
2861
Transceiver
10
NOW
862
2862
Transceiver
10
X
NOW
863
2863
Transceiver
9
NOW
864
2864
Transceiver
9
X
NOW
1-6 QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
FCT Logic - Continued
ad 25A
Part No,
Part No.
Rndco
BiS
Invert
Availa
543
2543
Latch Transceiver
8
NOW
544
2544
Latch Transceiver
8
X
NOW
2952
292052
Registered Transceiver
8
NOW
2953
292053
Registered Transceiver
8
X
NOW
646
2646
Registered Transceiver
8
NOW
648
2648
Registered Transceiver
8
X
NOW
651
RonictoroH Tranc/",oiv/or
neyioteitfu i icuioiscivci
Q
O
MOW
652
2652
Registered Transceiver
8
X
NOW
138
-
3-8 Decoder, Neg Out
X
NOW
139
-
Dual 2-4 Decoder, Neg Out
X
NOW
£00
o o uecoaer, ros vjui
Mf\VA/
INUW
239
-
Dual 2-4 Decoder, Pos Out
NOW
151
2151
8-input Multiplexer
1
NOW
153
2153
Dual 4-input Multiplexer
2
NOW
157
2157
Quad 2-input Multiplexer
4
NOW
158
2158
Quad 2-input Multiplexer
4
X
NOW
161
2161
4-bit Synchronous Counter
4
NOW
163
2163
4-bit Synchronous Counter
4
NOW
191
2191
4-bit Up/Down Counter
4
1Q92
193
2193
4-bit Up/Down Counter
4
1Q92
299
2299
8-bit Universal Shift Register
8
1Q92
280
Parity Generator
9
NOW
521
Identity Comparator
8
NOW
1280
Registered Parity Generator
9
NOW
QUALITY SEMICONDUCTOR INC.
1-7
GENERAL INFORMATION
1-8
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
—
NUMERICAL PRODUCT INDEX
Part No. Datasheet
29FCT2052 29FCT52
29FCT2053 29FCT52
29FCT2520 29FCT520
29FCT2521 29FCT520
29FCT52 29FCT52
29FCT520 29FCT520
29FCT521 29FCT520
29FCT53 29FCT52
FCT1280
FCT280
FCT138
FCT138
FCT139
FCT138
FCT151
FCT151
FCT153
FCT153
FCT157
FCT157
FCT158
FCT157
FCT161
FCT161
FCT163
FCT161
FCT191
FCT191
FCT193
FCT193
FCT2151
FCT151
FCT2153
FCT153
FCT2157
FCT157
FCT2158
FCT157
FCT2161
FCT161
FCT2163
FCT161
FCT2191
FCT191
FCT2193
FCT193
FCT2240
FCT240
FCT2241
FCT240
FCT2244
FCT240
FCT2245
FCT245
FCT2273
FCT273
FCT2299
FCT299
FCT2373
FCT373
FCT2374
FCT374
FCT2377
FCT377
FCT238
FCT138
FCT239
FCT139
Register Transceiver
Register Transceiver
Pipeline Register
Pipeline Register
Register Transceiver
Pipeline Register
Pipeline Register
Register Transceiver
Parity Generator/Checker
3- >8 Decoder, Neg Output
Dual 2->4 Decoder, Neg Output
8-input Multiplexer
Dual 4-input Multiplexer
Quad 2-input Multiplexer
Quad 2-input Multiplexer
4- bit Synchronous Counter
4-bit Synchronous Counter
4-bit Up/Down Counter
4-bit Up/Down Counter
8-input Multiplexer
Dual 4-input Multiplexer
Quad 2-input Multiplexer
Quad 2-input Multiplexer
4-bit Synchronous Counter
4-bit Synchronous Counter
4-bit Up/Down Counter
4-bit Up/Down Counter
Buffer
Buffer
Buffer
Transceiver
Register with Clear
8-bit Universal Shift Register
Latch
Register
Register with Clock Enable
3->8 Decoder, Pos Output
Dual 2->4 Decoder, Pos Output
•
Output Drive Page
Bits invert 222
8 X 4-27
8 X X 4-27
8 X 4-35
8 X 4-35
8 4-27
8 4-35
8 4-35
8 X 4-27
9 4-115
3 X 4-43
2 X 4-43
1 4-55
2 4-61
4 4-67
4 X 4-67
4 4-73
4 4-73
4 4-81
4 4-89
1 X 4-55
2 X 4-61
4 X 4-67
4 X X 4-67
4 X 4-73
4 X 4-73
4 X 4-81
4 X 4-89
8 X X 4-97
8 X 4-97
8 X 4-97
8 X 4-103
8 X 4-109
8 X 4-123
8 X 4-129
8 X 4-135
8 X 4-141
3 4-43
2 4-49
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
Output
Drive
Part No.
Data Sheet
Bits
Invert
25Q
Page
FCT240
FCT240
Buffer
8
X
4-97
FCT241
FCT240
Buffer
8
4-97
FCT244
FCT240
Buffer
8
4-97
FCT245
FCT245
Transceiver
8
4-103
FCT2540
FCT540
Buffer
8
X
4-153
FCT2541
FCT540
Buffer
8
X
4-153
FCT2543
FCT543
Latch Transceiver
8
X
4-159
FCT2544
FCT543
Latch Transceiver
8
X
X
4-159
FCT2573
FCT573
Latch
8
4-167
FCT2574
FCT574
Register
8
X
4-173
FCT2646
FCT646
Register Transceiver
8
X
4-179
FCT2648
FCT646
Register Transceiver
8
X
X
4-179
FCT2651
FCT651
Register Transceiver
8
X
X
4-187
FCT2652
FCT651
Register Transceiver
8
X
4-187
FCT273
FCT273
Register with Clear
8
4-109
FCT280
FCT280
Parity Generator/Checker
9
4-115
FCT2821
FCT821
Register
10
X
4-195
FCT2823
FCT821
Register
9
X
4-195
FCT2825
FCT821
Register
8
X
4-195
FCT2827
FCT827
Buffer
10
X
4-205
FCT2828
FCT827
Buffer
10
X
X
4-205
FCT2833
FCT833
Transceiver w/ Reg. Parity
8
X
4-211
FCT2841
FCT841
Latch
10
X
4-213
FCT2843
FCT841
Latch
9
X
4-213
FCT2845
FCT841
Latch
8
X
4-213
FCT2853
FCT853
Transceiver w/ Latched Parity
8
X
4-211
FCT2861
FCT861
Transceiver
10
X
4-223
FCT2862
FCT861
Transceiver
10
x
x
4-223
FCT2863
FCT861
Transceiver
9
x
4-223
FCT2864
FCT861
Transceiver
9
X
X
4-223
FCT299
FCT299
8-bit Universal Shift Register
8
4-123
FCT373
FCT373
Latch
8
4-129
FCT374
FCT374
Register
8
4-135
FCT377
FCT377
Register with Clock Enable
8
4-141
FCT521
FCT521
8-bit Equal Comparator
8
4-147
FCT540
FCT540
Buffer
8
X
4-153
FCT541
FCT540
Buffer
8
4-153
FCT543
FCT543
Latch Transceiver
8
4-159
FCT544
FCT543
Latch Transceiver
8
X
4-159
FCT573
FCT573
i_atcn
8
4-167
FCT574
FCT574
Register
8
4-173
FCT646
FCT646
Register Transceiver
8
4-179
FCT648
FCT646
Register Transceiver
8
X
4-179
FCT651
FCT651
Register Transceiver
8
X
4-187
FCT652
FCT651
Register Transceiver
8
4-187
FCT821
FCT821
Register
10
4-195
FCT823
FCT821
Register
9
4-195
FCT825
FCT821
Register
8
4-195
FCT827
FCT827
Buffer
10
4-205
FCT828
FCT827
Buffer
10
X
4-205
FCT833
FCT833
Transceiver w/ Reg. Parity
8
4-211
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
Output Drive
Part No.
Datasheet
Desoitfjn
Bits
Invert
25Q
Page
FCT841
FCT841
Latch
10
4-213
FCT843
FCT841
Latch
9
4-213
FCT845
FCT841
Latch
8
4-213
FCT853
FCT833
Transceiver with Latched Parity
8
4-211
FCT861
FCT861
Transceiver
10
4-223
FCT862
FCT861
Transceiver
10
X
4-223
FCT863
FCT861
Transceiver
9
4-223
FCT864
FCT861
Transceiver
9
X
4-223
Port Kb-t
uaaoneei
Rr+C
PIS
uensny
—
Page
QS7201
QS7201
512X9 FIFO
9
4.5 K
3-5
Uo/ZUZ
Ub/201
IK A 9 HKJ
9
9K
3-5
QS7203
QS7204
2X9 FIFO
9
18K
3-21
QS7204
QS7204
4KX9FIFO
9
36K
3-21
QS7211
QS7211
512X9 FIFO with OE
9
4.5K
3-39
QS7212
QS721 1
1K X9 FIFO with OE
II\ f\ J 1 II \— / TV Hll w 1
g
9K
3-39
QS7223
QS7224
2K X 9 FIFO, Clocked l/F
9
18K
3-53
WO / ££H
Y q cicn Plnrkorl l/P
*H\ A 57 rlr\J, V^IOulNeU l/r
Q
OOf\
o-oo
QS7306
QS7306
64K X 4 FIFO, Clocked l/F
4
256K
3-67
QS7316
QS7316
64K X 4 Burst Mode Dual Port RAM
4
256K
3-69
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
Part No.
Data Sheet
D69CfCbon
Bits
Densitv
Page
QS812880
QS812880
128Kx8 SRAM
8
1024K
2-129
OS8768
OS8768
4Kx4 SRAM
4
16K
2-5
QS8769
QS8769
4Kx4 SRAM Fast Chip Select
4
16K
2-13
QS8780
QS8780
4Kx4 Cache Tag RAM with Reset
4
16K
2-21
OS83280
OS83280
32Kx8 SRAM
8
256K
2-81
OSR12RT
12Kx8 SRAM Fa<;t Addrp«;s Bit
8
256K
2-89
^PKyR. SRAM 1 nw Pnwpr
oc i\AO o n amvi , luw ruwci
a
o
2-Q1
vj< o o o c o c?
^?Ky« SRAM Fa<tf Chin Kplprt
a
o
2-QQ
QS83290
QS83290
32Kx9 SRAM
9
288K
2-101
QS83291
QS83291
32Kx9 SRAM, Burst Mode
9
288K
2-103
OS86440
OS8B440
R4Kx4 SRAM Common I/O
4
256K
2-105
OS86442
OS8G442
R4Kx4 SRAM Carhp Tan
4
256K
2-113
QS86444
QS86444
64Kx4 SRAM, Separate I/O
4
256K
2-115
QS86446
QS86446
64Kx4 SRAM, Output Enable
4
256K
2-117
QS86447
OS86447
64Kx4 SRAM Address Latch
4
256K
2-125
QS86448
OS86448
R4Ky4 SRAM AriHrpt;^ Rpnfctpr
4
256K
2-127
OS86449
OS8B444
64K*4 SRAM Spnaratp I/O
4
2-1 15
QS881 60
8Ky1R f^arhp Plata SRAM
1 28K
9-R7
QS88180
QS88180
8Kx18 Cache Data SRAM
18
128K
2-67
QS88181
QS88181
8Kx18 Burst Mode SRAM
18
144K
2-77
OSRfll R9
OSRH1 R?
RKV1R Carho Tan SRAM
or\A io oauiic i ay onMivi
1 ft
144K
QS8881
QS8881
16Kx4 SRAM, Separate I/O
4
64K
2-31
QS8882
QS8881
16Kx4 SRAM, Separate I/O
4
64K
2-31
QS8883
QS8883
16Kx4 SRAM, Tag
4
64K
2-41
QS8885
QS8886
16Kx4 SRAM, OE
4
64K
2-51
QS8886
QS8886
16Kx4SRAM, OE, 2 CS
4
64K
2-51
QS8888
QS8888
16Kx4 SRAM, 22 pin
4
64K
2-59
Outout Drive
Part No.
Datasheet
Bits.
Invert
Page
QST3383
QST3383/53
QuickSwitch Bus Exchange
10
5-17
QST3384
QST3384/54
QuickSwitch Bus Connect
10
X
5-23
QST3353
QST3383/53
QuickSwitch Bus Exchange
10
5-17
QST3354
QST3384/54
QuickSwitch Bus Connect
10
X
5-23
1-12
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
SRAM
QS8XXX XXX XX X
Processing
H Package type
_| Speed
(Access time)
-j Device Type
Processing;
Blank - Standard Commercial, 0-70 °C
B - MIL-STD883, -55°C to +125 °C
M - Commercial, -55°C to +1 25 °C
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
QUALITY SEMICONDUCTOR INC.
1-13
GENERAL INFORMATION
=^^^= — —
FIFO
QS7XXX XXX XX
Processing
I Package type
I Speed (Access time)
Device Type
Processing:
Blank - Standard Commercial, 0-70 °C
B - MIL-STD883, -55°C to +1 25 °C
M - Commercial, -55°C to +125 °C
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
1-14
QUALITY SEMICONDUCTOR INC.
GENERAL INFORMATION
ORDERING INFORMATION
FCT-T
QSXXFCT _XXX X I XX X
QS29FCT _XXX X I XX X
Processing
H Package type
FCT-T
Designation
1 Speed grade
-\ Device type
54 -55 to +125 °C
>70°C
-4 54 -55 tc
I 74 oto;
:
Processing
i Package type
_| FCT-T Designation
H Speed grade
~\ Device type
Family
Designation
Speed Grades;
Blank - Standard
A
B
C
D
Processing:
Blank
B
M
Standard Commercial, 0-70 °C
MIL-STD 883 Military -55°C to +125 °C
Commercial, -55°C to +125 °C (29FCT Only)
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
5 1 - Small Outline IC, 1 50 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
QUALITY SEMICONDUCTOR INC.
1-15
GENERAL INFORMATION
ORDERING INFORMATION
QUICKSWITCH
QSXXQST XXXX XX X
1
1
1
1
-| Processing
Package type
Device type
54
74
-55to+125°C
0 to70 °C
processing;
Blank - Standard Commercial, 0-70 °C
B - MIL-STD 883, -55°C to +1 25 °C
M - Commercial, -55°C to +125 °C
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
1-16
QUALITY SEMICONDUCTOR INC.
Cross Reference
STATIC RAM
IDT
IDT6168LA-10
IDT6168LA-12
IDT6168LA-15
IDT6168LA-20
IDT6168LA-25
IDT6168LA-35
IDT6168SA-10
IDT6168SA-12
IDT6168SA-15
IDT6168SA-20
IDT6168SA-25
IDT6168SA-35
IDT6178S-12
IDT6178S-15
IDT6178S-20
IDT6178S-25
IDT6198L15
IDT6198L20
IDT6198L25
IDT6198L35
IDT6198S15
IDT6198S20
IDT6198S25
IDT6198S35
IDT61B98-10
IDT61B98-12
IDT71256L-15
IDT71256L-20
IDT71256L-25
IDT71256L-30
IDT71256L-45
IDT71256S-15
IDT71256S-20
IDT71256S-25
IDT71256S-30
IDT71256S-45
IDT71258L-15
IDT71258L-20
IDT71258L-25
IDT71258L-35
IDT71258S-15
IDT71258S-20
IDT71258S-25
IDT71258S-35
IDT71681-10
IDT71681-12
IDT71681-15
IDT71681-20
IDT71681-25
IDT71681-35
I DT71 682-10
IDT71 682-12
IDT71682-15
IDT71 682-20
QS8768-10
QS8768-12
QS8768-15
QS8768-20
QS8768-25
QS8768-35
QS8768-10
QS8768-12
QS8768-15
QS8768-20
QS8768-25
QS8768-35
QS8780-12
QS8780-15
QS8780-20
QS8780-25
QS8886-15
QS8886-20
QS8886-25
QS8886-35
QS8886-15
QS8886-20
QS8886-25
QS8886-35
QS8886-10
QS8886-12
QS83280-15
QS83280-20
QS83280-25
QS83280-30
QS83280-45
QS83280-15
QS83280-20
QS83280-25
QS83280-30
QS83280-45
QS86440-15
QS86440-20
QS86440-25
QS86440-35
QS86440-15
QS86440-20
QS86440-25
QS86440-35
QS8761-10
QS8761
QS8761
QS8761
QS8761
QS8761-35
QS8762-10
QS8762-12
QS8762-15
QS8762-20
-12
-15
-20
-25
IDT
QSI
(continued)
I DT71 682-25
QS8762
25
I DT71 682-35
QS8762
■35
IDT7188L15
QS8888
•15
IDT7188L20
QS8888
■20
IDT7188L25
QS8888
■25
IDT7188L35
QS8888
■35
IDT7188S15
QS8888
■15
IDT7188S20
QS8888
■20
IDT7188S25
QS8888
■25
IDT7188S35
QS8888
■35
IDT71981S15
QS8881
■15
IDT71981S20
QS8881
■20
IDT71981S25
QS8881
■25
IDT71981S35
QS8881
■35
IDT71982S15
QS8882
■15
IDT71982S20
QS8882
■20
IDT71982S25
QS8882
■25
IDT71982S35
QS8882
■35
IDT7198L15
QS8885
•15
IDT7198L20
QS8885
■20
inT71QRI 25
QS8885
■25
IDT7198L35
QS8885
■35
IDT7198S15
QS8885
■15
IDT7198S20
QS8885
■20
IDT7198S25
QS8885
■25
IDT7198S35
QS8885
■35
IDT71B256-15
QS83280-15
IDT71B256-20
QS83280-20
IDT71B258S-15
QS86440-15
IDT71B258S-20
QS86440-20
CYPRESS
QSI
CY7C161-20
QS8881
•20
CY7C161-25
QS8881
25
CY7C161-35
QS8881
•35
CY7C161A-15
QS8881
■15
CY7C161A-20
QS8881
•20
CY7C161A-25
QS8881
■25
CY7C161A-35
QS8881
■35
CY7C1 62-20
QS8882
•20
CY7C 162-25
QS8882
■25
CY7C1 62-35
QS8882
■35
CY7C162A-15
QS8882
•15
CY7C162A-20
QS8882
■20
CY7C162A-25
QS8882
•25
CY7C162A-35
QS8882
■35
CY7C164-15
QS8888
■15
CY7C 164-20
QS8888
•20
CY7C 164-25
QS8888
•25
CY7C1 64-35
QS8888
•35
CY7C164A-15
QS8888
•15
CY7C164A-20
QS8888
•20
QUALITY SEMICONDUCTOR INC. 1-17
Cross Reference
O T r n too
u o i
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OSI
(Continuod)
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HM6788-15
QS8888-15
MCM6208-25
QS86440-25
HM6788-20
QS8888-20
MCM6208-35
QS86440-35
HM6788-25
QS8888-25
MCM6209-15
QS86446-15
HM6788-35
QS8888-35
M CM 6209-20
QS86446-20
HM6789H-12
QS8886-12
MCM6209-25
QS86446-25
HM6789H-15
QS8886-15
MCM6209-35
QS86446-35
HM6789H-20
QS8886-20
MCM6268-20
QS8768-20
HM6789H-25
QS8886-25
M CM 6268-25
QS8768-25
HM6789H-35
QS8886-35
MCM6268-35
QS8768-35
MCM6269-20
QS8769-20
MCM6269-25
QS8769-25
1-18
QUALITY SEMICONDUCTOR INC.
Cross Reference
—
STATIC RAM
MICRON
QSI
PERFORMANCE
QSI
(Continued)
(Continued)
MCM6269-35
QS8769-35
P4C188-15
QS8888-15
MCM6288-12
QS8888-12
P4C1 88-20
QS8888-20
M CM 6288- 15
QS8888-15
P4C1 88-25
QS8888-25
MCM6288-20
QS8888-20
P4C 188-35
QS8888-35
MCM6288-25
QS8888-25
P4C198-15
QS8886-15
MCM6288-35
QS8888-35
P4C1 98-20
QS8886-20
MCM6290-12
QS8886-12
P4C1 98-25
QS8886-25
MCM6290-15
QS8886-15
P4C 198-35
QS8886-35
MCM6290-20
QS8886-20
P4C1981-15
QS8881-15
MCM6290-25
QS8886-25
P4C1981-20
QS8881-20
MCM6290-35
QS8886-35
P4C1981-25
QS8881-25
P4C1982-15
QS8882-15
PERFORMANCE
QSI
P4C1 982-20
QS8882-20
P4C1 982-25
QS8882-25
P4C1 258-20
QS86440-20
P4C198A-15
QS8885-15
P4C1 258-25
QS86440-25
P4C198A-20
QS8885-20
P4C1 258-35
QS86440-35
P4C198A-25
QS8885-25
P4C168-12
QS8768-12
P4C168-15
QS8768-15
Tl
QSI
P4C1 68-20
QS8768-20
P4C1 68-25
QS8768-25
SN74ACT2140A
QS881 80-25
P4C1 68-35
QS8768-35
P4C1681-12
QS8761-12
TOSHIBA
QSI
P4C1681-15
QS8761-15
P4C1681-20
QS8761-20
TC55416-15
QS8888-15
P4C1681-25
QS8761-25
TC55416-20
i QS8888-20
P4C1681-35
QS8761-35
TC55416-25
QS8888-25
P4C1682-12
QS8762-12
TC55416-35
QS8888-35
P4C1682-15
QS8762-15
TC55417-15
QS8886-15
P4C1 682-20
QS8762-20
TC55417-20
QS8886-20
P4C1 682-25
QS8762-25
TC55417-25
QS8886-25
P4C1 682-35
QS8762-35
TC55417-35
QS8886-35
-
QUALITY SEMICONDUCTOR INC. 1-19
Cross Reference
STATIC RAM
1-20
QUALITY SEMICONDUCTOR INC.
Cross Reference
a win
AMU
An-»7oni -ion
Am / d\j l -i <L\)
fifi
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oc
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25
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QS7203
■15
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1-21
Cross Reference
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1-22
QUALITY SEMICONDUCTOR INC.
Cross Reference
HARRIS
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(Continued)
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QUALITY SEMICONDUCTOR INC.
1-23
Cross Reference
IDT
(Continued)
IDT74FCT245T
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IDT
(Continued)
IDT74FCT540
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1-24
QUALITY SEMICONDUCTOR INC.
Cross Reference
FCT-T LOGIC
IDT
(Continued)
IDT74FCT825B
I DT74FCT825BT
IDT74FCT825C
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(Continued)
I DT74FBT374AT
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NATIONAL
74FCT138
74FCT138A
74FCT240
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74FCT244
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74FCT533A
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QUALITY SEMICONDUCTOR INC.
1-25
Cross Reference
=
NATIONAL
(Continued)
74FCT573
74FCT573A
74FCT574
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74FCT646
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74FCT821A
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74FCT845B
74ACT138
74ACT139
74ACT151
74ACT153
74ACT157
74ACT158
74ACT1 61
74ACT1 63
74ACT191
74ACT240
74ACT241
74ACT244
74ACT245
74ACT251
74ACT253
74ACT257
74ACT258
74ACT273
74ACT299
74ACT373
74ACT374
74ACT377
74ACT521
74ACT534
74ACT573
74ACT574
74ACT646
74ACT821
74ACT823
74ACT825
74ACT841
74ACT843
74ACT845
QSI
QS74FCT573T
QS74FCT573AT
QS74FCT574T
QS74 FCT574AT
QS74FCT646T
QS74FCT646AT
QS74FCT821AT
QS74FCT821BT
QS74FCT823AT
QS74FCT823BT
QS74FCT825AT
QS74FCT825BT
QS74FCT827AT
QS74FCT827BT
QS74FCT841AT
QS74FCT841BT
QS74FCT843AT
QS74FCT843BT
QS74FCT845AT
QS74FCT845BT
QST4FCT138T
QS74FCT139T
QS74FCT151T
QS74FCT153T
QS74FCT157T
QS74FCT158T
QS74FCT161T
QS74FCT163T
QS74FCT191T
QST4FCT240T
QST4FCT241T
QST4FCT244T
QST4FCT245T
QS74FCT251T
QS74FCT253T
QS74FCT257T
QS74FCT258T
QS74FCT273T
QS74FCT299T
QST4FCT373T
QST4FCT374T
QS74FCT377T
QS74FCT521T
QS74FCT534T
QS74FCT573T
QS74FCT574T
QS74FCT646T
QS74FCT821AT
QS74FCT823AT
QS74FCT825AT
QS74FCT841AT
QS74FCT843AT
QS74FCT845AT
NATIONAL
(Continued)
74ACTQ153
74ACTQ240
74ACTQ241
74ACTQ244
74ACTQ245
74ACTQ273
74ACTQ373
74ACTQ374
74ACTQ377
74ACTQ533
74ACTQ534
74ACTQ543
74ACTQ544
74ACTQ573
74ACTQ574
74ACTQ646
74ACTQ821
74ACTQ827
74ACTQ841
74ACTQ843
PERFORMANCE
P29PCT520
P29PCT520A
P29PCT521
P29PCT521A
P29PCT52A
P29PCT52B
P29PCT53A
P29PCT53B
P74PCT138
P74PCT138A
P74PCT138B
P74PCT139
P74PCT139A
P74PCT139B
P74PCT157A
P74PCT157B
P74PCT158A
P74PCT158B
P74PCT161
P74PCT161A
P74PCT163
P74PCT163A
P74PCT240
P74PCT240A
P74PCT241
P74PCT241A
P74PCT244
P74PCT244A
P74PCT245
P74PCT245A
QSI
QS74FCT153T
QST4FCT240T
QST4FCT241T
QST4FCT244T
QST4FCT245T
QS74FCT273T
QST4FCT373T
QST4FCT374T
QS74FCT377T
QS74FCT533T
QS74FCT534T
QS74FCT543T
QS74FCT544T
QS74FCT573T
QS74FCT574T
QS74FCT646T
QS74FCT821 AT
QS74FCT827AT
QS74FCT841 AT
QS74FCT843AT
QSI
QS29FCT520AT
QS29FCT520BT
QS29FCT521 AT
QS29FCT521BT
QS29FCT52AT
QS29FCT52BT
QS29FCT53AT
QS29FCT53BT
QS74FCT138T
QS74FCT1 38AT
QS74FCT138CT
QS74FCT139T
QS74FCT139AT
QS74FCT139CT
QS74FCT157T
QS74FCT157AT
QS74FCT158T
QS74FCT158AT
QS74FCT161T
QS74FCT161 AT
QS74FCT1 63T
QS74FCT1 63AT
QS74FCT240T
QS74FCT240AT
QST4FCT241T
QS74FCT241 AT
QST4FCT244T
QS74FCT244AT
QST4FCT245T
QS74FCT245AT
1-26
QUALITY SEMICONDUCTOR INC.
Cross Reference
PERFORMANCE
(Continued)
P74PCT257A
P74PCT257B
P74PCT258A
P74PCT258B
P74PCT273
P74PCT273A
P74PCT299
P74PCT299A
P74PCT373
P74PCT373A
P74PCT374
P74PCT374A
P74PCT377
P74PCT377A
P74PCT521
P74PCT521A
P74PCT521B
P74PCT533
P74PCT533A
P74PCT534
P74PCT534A
P74PCT543
P74PCT543A
P74PCT544
P74PCT544A
P74PCT573
P74PCT573A
P74PCT574
P74PCT574A
P74PCT640
P74PCT640A
P74PCT646
P74PCT646A
P74PCT648
P74PCT648A
P74PCT651
P74PCT651A
P74PCT652
P74PCT652A
P74PCT821A
P74PCT821B
P74PCT823A
P74PCT823B
P74PCT825A
P74PCT825B
P74PCT827A
P74PCT827B
P74PCT828A
P74PCT828B
P74PCT841A
P74PCT841B
P74PCT843A
P74PCT843B
QSI
QS74FCT257T
QS74FCT257AT
QS74FCT258T
QS74FCT258AT
QS74FCT273T
QS74FCT273AT
QS74FCT299T
QS74FCT299AT
QST4FCT373T
QS74FCT373AT
QST4FCT374T
QS74FCT374AT
QS74FCT377T
QS74FCT377AT
QS74FCT521T
QS74FCT521 AT
QS74FCT521BT
QS74FCT533T
QS74FCT533AT
QS74FCT534T
QS74FCT534AT
QS74FCT543T
QS74FCT543AT
QS74FCT544T
QS74FCT544AT
QS74FCT573T
QS74FCT573AT
QS74FCT574T
QS74FCT574AT
QS74FCT640T
QS74FCT640AT
QS74FCT646T
QS74FCT646AT
QS74FCT648T
QS74FCT648AT
QS74FCT651T
QS74FCT651AT
QS74FCT652T
QS74FCT652AT
QS74FCT821AT
QS74FCT821BT
QS74FCT823AT
QS74FCT823BT
QS74FCT825AT
QS74FCT825BT
QS74FCT827AT
QS74FCT827BT
QS74FCT828AT
QS74FCT828BT
QS74FCT841AT
QS74FCT841BT
QS74FCT843AT
QS74FCT843BT
SIGNETICS
74ABT2952
74ABT2953
74ABT240
74ABT241
74ABT244
74ABT245
74ABT373
74ABT374
74ABT377
74ABT533
74ABT534
74ABT540
74ABT541
74ABT543
74ABT544
74ABT573
74ABT574
74ABT646
74ABT648
74ABT651
74ABT652
74ABT821
74ABT823
74ABT825
74ABT827
74ABT841
74ABT843
74ABT845
74ABT861
74ABT863
Tl
SN74ABT2952
SN74ABT2953
SN74ABT2240
SN74ABT2241
SN74ABT2244
SN74ABT240
SN74ABT241
SN74ABT244
SN74ABT245
SN74ABT299
SN74ABT373
SN74ABT374
SN74ABT533
SN74ABT534
SN74ABT540
SN74ABT541
SN74ABT573
SN74ABT574
SN74ABT646
SN74ABT648
SN74ABT651
QSI
QS29FCT52BT
QS29FCT53BT
QS74FCT240CT
QS74FCT241CT
QS74FCT244CT
QS74FCT245CT
QS74FCT373CT
QS74FCT374CT
QS74FCT377CT
QS74FCT533CT
QS74FCT534CT
QS74FCT540AT
QS74FCT541AT
QS74FCT543AT
QS74FCT544AT
QS74FCT573AT
QS74FCT574AT
QS74FCT646CT
QS74FCT648CT
QS74FCT651AT
QS74FCT652AT
QS74FCT821BT
QS74FCT823BT
QS74FCT825BT
QS74FCT827BT
QS74FCT841BT
QS74FCT843BT
QS74FCT845BT
QS74FCT861BT
QS74FCT863BT
QSI
QS29FCT52BT
QS29FCT53BT
QS74FCT2240CT
QS74FCT2241 CT
QS74FCT2244CT
QS74FCT240CT
QS74FCT241CT
QS74FCT244CT
QS74FCT245CT
QS74FCT299AT
QS74FCT373CT
QS74FCT374CT
QS74FCT533CT
QS74FCT534CT
QS74FCT540AT
QS74FCT541 AT
QS74FCT573AT
QS74FCT574AT
QS74FCT646CT
QS74FCT648CT
QS74FCT651 AT
QUALITY SEMICONDUCTOR INC.
1-27
Cross Reference
Tl
(Continued)
SN74ABT652
SN74ABT821
SN74ABT823
SN74ABT825
SN74ABT827
SN74ABT828
SN74ABT841
SN74ABT843
SN74ABT845
SN74ABT861
SN74ABT864
SN74BCT2952
SN74BCT2953
SN74BCT240
SN74BCT241
SN74BCT244
SN74BCT245
SN74BCT299
SN74BCT373
SN74BCT374
SN74BCT533
SN74BCT534
SN74BCT540
SN74BCT541
SN74BCT543
SN74BCT544
SN74BCT573
SN74BCT574
SN74BCT646
SN74BCT648
SN74BCT651
SN74BCT652
SN74BCT821
SN74BCT823
SN74BCT825
SN74BCT828
SN74BCT2240
SN74BCT2241
SN74BCT2244
SN74BCT2827
SN74BCT2828
QSI
QS74FCT652AT
QS74FCT821BT
QS74FCT823BT
QS74FCT825BT
QS74FCT827BT
QS74FCT828BT
QS74FCT841BT
QS74FCT843BT
QS74FCT845BT
QS74FCT861BT
QS74FCT864BT
QS29FCT52AT
QS29FCT53AT
QST4FCT240T
QST4FCT241T
QST4FCT244T
QST4FCT245T
QS74FCT299T
QST4FCT373T
QST4FCT374T
QS74FCT533T
QS74FCT534T
QS74FCT540T
QS74FCT541T
QS74FCT543T
QS74FCT544T
QS74FCT573T
QS74FCT574T
QS74FCT646T
QS74FCT648T
QS74FCT651T
QS74FCT652T
QS74FCT821AT
QS74FCT823AT
QS74FCT825AT
QS74FCT828AT
QS74FCT2240T
QS74FCT2241T
QS74FCT2244T
QS74 FCT2827AT
QS74FCT2828AT
QUALITY SEMICONDUCTOR INC.
General Information 1
FIFO Memory Products 3
FCT-T Logic Products 4
QuickSwitch Products 5
Application Notes 6
Quality And Reliability 7
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
QUALITY SEMICONDUCTOR INC.
SRAM Table of Contents
STATIC RAM DATA SHEETS
Page
SRAM Ordering Information 2-3
SRAM Test Cinfiguration 2-4
QS8768 4Kx4 SRAM in 20 pins 2-5
QS8769 4Kx4 SRAM in 20 pins with fast CS" 2-13
QS8780 4Kx4 Cache Tag RAM with Reset 2-21
QS8881/2 16Kx4 SRAM with Separate I/O 2-31
QS8883 1 6Kx4 Cache Tag SRAM 2-41
QS8885/6 1 6Kx4 SRAM with Output Enable 2-51
QS8888 1 6Kx4 SRAM in 22 pins 2-59
QS88180/60 8Kx18/16 SRAM 2-67
QS88181 8Kx1 8 Burst Mode SRAM 2-77
QS881 82 8Kx18 Cache TAG SRAM 2-79
QS83280 32Kx8 SRAM 2-81
QS83283 32Kx8 SRAM with Fast Address bit 2-89
QS83285 32Kx8 Low Power SRAM 2-91
QS83289 32Kx8 SRAM with Fast Chip Select 2-99
QS83290 32Kx9 SRAM 2-101
QS83291 32Kx9 Burst Mode SRAM 2-103
QS86440 64Kx4 SRAM 2-105
QS86442 64Kx4 Cache TAG SRAM 2-113
QS86444/9 64Kx4 SRAM with Separate I/O 2-115
QS86446 64Kx4 SRAM with Output Enable 2-117
QS86447 64Kx4 SRAM with Address Latch 2-125
QS86448 64Kx4 SRAM with Address Register 2-127
QS81280 128Kx8 SRAM 2-129
QUALITY SEMICONDUCTOR INC. 2-1
SRAM Table of Contents
=
2-2
QUALITY SEMICONDUCTOR INC.
SRAM Ordering Information
QS8XXX XXX XX
Processing:
Blank - Standard
B - MIL-STD 883
Temperature
Range
-\ Package type
_j Speed
(Access time)
Device Type
P
D
L
SO
S1
z
Q
Package Type:
Plastic DIP, 300 mi
Ceramic DIP, 300 mil
Leadless Ceramic Chip Carrier
Small Outline IC, 300 mil
Small Outline IC, 150 mil
Plastic ZIP
QSOP, Quarter Size Outline Package, 150 mil
QUALITY SEMICONDUCTOR INC.
2-3
To Output Pin
O
255 n
SRAM Test Configuration
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures
+5V
+5V
To Output Pin
o-
48 0Q
* Includes jig & scope
capacitance
" for: tHZ, tLZ,
twz.tow
/TN 30 pF*
255 a
5pF*
Figure 1. Output test loads for: 4Kx4, 16Kx4, 64Kx4, 32Kx8
&128Kx8 SRAMs (Except Low-Power)
+5V
667 a
100
+5V
To Output Pin y 1 Kfl Jo
Output Pin
O
667
1KQ
* Includes jig & scope
capacitance
" for: tHZ, tLZ,
twz.tow
5pF"
Figure 2. Output test loads for:8Kx18 and 8Kx16 SRAMs
+5V
To Output Pin
O
990 Q
1.8KO
+5V
To Output Pin
O-
1.8KQ
990
* Includes jig & scope
** for: tHZ, tLZ,
twz,tow
5pF"
Figure 3. Output test loads for Low-Power 32Kx8 SRAMs
QUALITY SEMICONDUCTOR INC.
QS8768
Q
FEATURES/BENEFITS
High-Speed CMOS
. 4Kx4 SRAM
with Common I/O
QS8768
1 High Speed Access and Cycle times
10ns/12ns/15ns/20ns/25nsCommIrcial
15ns/20ns/25ns/35ns Military °mmerC,al
TTL compatible I/O
Low power high-speed QCMOS™ technoloav
Milrtary product compliant to MIL-STD-f«Tr?E B
6-Transistor cell for high reliability
Idea tor reliable.dense memory systems
Available in 20-pin DIP, 20-Pin zip
20-pin 300 mil SOJ & 20-pin LCC
Low Standby current
JEDEC standard pinout
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Address
hi Q
DC 0
IS
16,384 BIT
MEMORY
ARRAY
QS8768
B
=
PIN CONFIGURATIONS
PDIP, SOJ
ZIP
A8( 1*
A10 ( 3
VCC( 5
A1 C 7
A3( 9
A5 ( 11
A7 ( 13
GND ( 15
I/O 1 ( 17
l/0 3( 19
2 ) A9
) A11
6 ) AO
8 ) A2
10 ) A4
) A6
) CS
) WE
) I/O 2
) I/O 4
ALL PINS TOP VIEW
B g g! 2 g
:
PIN DESCRIPTION
FUNCTION TABLE
Pin Name
I/O
Function
C3
WE
I/O
Power
Function
A
I
Address
H
X
HighZ
Standby
Deselect
1/01 - 1/04
I/O
Data
L
H
Data Out
Active
Read
C5
I
Chip Select
L
L
Data In
Active
Write
WE
I
Write Enable
■BS
2-6
QUALITY SEMICONDUCTOR INC.
QS8768
=
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground
DC Output Voltage Vq -0.5V
DC Input Voltage V| -0.5V
AC Input Voltage (for a pulse width <20 ns)
DC Output Current Max. sink current/pin
DC Output Current Max. source current/pin
Tqias Temperature Under Bias, COM
TSTG Storage Temperature, COM
TBIAS Temperature Under Bias, MIL
TSTG Storage Temperature, MIL
-0.5V to +7.0V
toVcc +0.5V
toVcc +0-5V
-3.0V
50 mA
30 mA
-65° to +125°C
-65°to+125°C
-65°tO+135°C
-65°to+155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta-+25°C, f-1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
pF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0 V PDIP Pkg.
7
pF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY
INC.
2-7
QS8768
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8 mA, Vcc = MIN
0.4
0.4
|l|
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
HA
| Ho |
Output Leakage
Vcc = MAX,
Vout = GNDtO Vcc
5
10
Notes:
1. Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-10
-12
1 5
-20 | -25/-35
Unit
c
M
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = 0
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS < Vil, f = fMAX
145
165
135
155
125
145
120
140
110
130
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS > Vih, f = f MAX
60
70
60
70
60
70
60
70
60
70
Isb1
Full Standby
Current, Vcc = MAX
Outputs open
CS>Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
15
20
2-8
QUALITY SEMICONDUCTOR INC.
QS8768
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(D
-10(3)
-12 (3)
-15
-20
-25
-35
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
10
-
12
-
15
-
19
-
25
-
35
-
t AA
Address
Access Time
-
10
-
12
-
15
-
19
-
25
-
35
tACS
Chip Select
Access Time
10
12
15
19
25
35
tOH
Output Hold from
Address Change
2
2
2
3
3
3
tCLZ
Chip Select to
Output in Low Z (2)
2
2
2
2
2
3
tCHZ
Chip Select to
Output in High Z (2)
4
5
7
8
10
15
tPU
Chip Select to
Power Up Time (2)
0
0
0
0
0
0
tPD
Chip Select to
Power Down Time (2)
10
12
15
19
25
35
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5%. Commercial Only-Preliminary Data.
■
QUALITY SEMICONDUCTOR INC.
2-9
QS8768
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbo.
Parameter
-10(3)
-12 (3)
-15
-20
-25
-35
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
twc
Write Cycle Time
10
12
15
19
25
35
tew
Chip Select Valid to
End of Write
8
10
13
17
20
30
tAW
Address Valid to
End of Write
8
10
13
17
20
30
t AS
Address
Setup Time
0
0
0
0
0
0
tWP
Write Pulse width
8
-
10
-
12
-
16
-
20
-
30
-
tWR
Write
Recovery Time
0
0
0
0
0
0
tDW
Data Valid to
End of Write
5
7
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
4
5
6
7
8
12
tow
Output Active from
End of Write (2)
2
2
2
2
2
3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
2-10
QUALITY SEMICONDUCTOR INC.
QS8768
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
tRC
C5
ADRS
_
J5L
-
^( ADDRESS VALID"
t AA
DATA OUT
x
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
U, tRC (5) *
ADRS
DATA OUT
ADDRESS VALID
t ACS
tHZ(4),
X data valid ^
tPU
Vex; SUPPLY Ice
CURRENT
Notes:
Isb
-JL
5k
1 . WE~is high for Read cycle.
2. " CS~is low for Read cycle #1 .
3. Address is valid to or coincident with CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
QUALITY SEMICONDUCTOR INC.
2-11
=
QS8768
=====
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
ADRS
WE
DATA OUT
DATA IN
twc
tAW
Sir-
tWR
^ S
t AS
tWP
t WZ (6)
~4
tDW
tow
DATA VALID
TIMING WAVEFORMS-WRITE CYCLE I
twc
ADRS "
C5
WE
DATA IN
tAW
tew
tDW
jntrolled timing)
3c
—
tWR
<« ►
« tDH ►
PATA VALIP
Notes:
1 . WE or must be high during address transitions.
2. A write occurs during the overlap of a low and a tow WE.
3. t WR is measured from the earlier of and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the CS tow transition occurs simultaneously with or after the WE tow transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
2-12
QUALITY SEMICONDUCTOR INC.
QS8769
Q
High-Speed CMOS
4Kx4 SRAM
with Fast Chip Select
QS8769
FEATURES/BENEFITS
High Speed Access and Cycle times
1 0ns/1 2ns/1 5ns/20ns/25ns Commercial
1 5ns/20ns/25ns/35ns Military
Non power down for fast Chip select access
5ns/6ns/8ns/10ns/12ns chip select access times
Low power, high-speed QCMOS™ technology
Military product compliant to MIL-STD-883
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
TTL compatible I/O
Available in 20-pin DIP, 20-Pin ZIP
20-pin 300 mil SOJ , 20-pin LCC
JEDEC standard pinout
=
DESCRIPTION
The QS8769 is a high-speed 16K SRAM with fast chip select organized as 4Kx4. The chip select
access time is fast since it does not power down the memory array when the chip is deselected. The
QS8769 is manufactured in a high-performance CMOS process, and it is based on a 6-transistor cell
design for high reliability of data retention. The high-speed access times of the QS8769 make it useful
in cache data RAM, cache tag RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP
and bit-slice systems. Low operating power and excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
41 A
C5
WE
16,384 BIT
MEMORY
ARRAY
j— >. Write
T<L) ri ,_i i—. Read
Read/Write Data I/O hH^-
I/O
QUALITY SEMICONDUCTOR INC.
2-13
QS8769
PIN CONFIGURATIONS
ZIP
PDIP, SOJ
ao d~i~
A10( 3
§ & § §
ALL PINS TOP VIEW
PIN DESCRIPTION
-
FUNCTION TABLE
Pin Name
I/O
Function
A
I
Address
1/01 - 1/04
I/O
Data
C5
I
Chip Select
WE
I
Write Enable
C5
WE
I/O
Power
Function
H
X
HighZ
Standby
Deselect
L
H
Data Out
Active
Read
L
L
Data In
Active
Write
1 1
SB
2-14
QUALITY SEMICONDUCTOR INC.
QS8769
s
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to Vqc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65°to+125°C
TSTG StorageTemperature.COM -65° to +125°C
TBIAS TemperatureUnderBias.MIL -65°to+135°C
TSTG StorageTemperature.MIL -65°to+155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Note: Capacitance is measured at characterization but not tested at final production.
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
pF
Cout
Output Capacitance
Vout = 0V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
QUALITY SEMICONDUCTOR INC.
2-15
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA, Vcc = MIN
0.4
0.4
IJi)
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
fiA
I Ho |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes: 1. Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-10
-12
1 5
-20
-25/-35
Unit
c
M
c
M
C
M
C
M
C
M
led
Static Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = 0
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = f MAX
145
165
135
155
125
145
120
140
110
130
2-16
QUALITY SEMICONDUCTOR INC.
QS8769
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vex; = 5.0V+10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-10(3)
-1 £.
(3)
-15
-20
-25
-35
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
1
READ CYCLE
tRC
Read Cycle Time
10
12
-
15
19
25
35
t AA
Address
10
-
12
15
19
25
35
Access Time
t ACS
Chip Select
5
6
8
10
12
17
Access Time
tOH
Output Hold from
Address Change
2
2
2
3
3
3
tCLZ
Chip Select to
Output in Low Z (2)
2
2
2
2
2
3
tCHZ
Chip Select to
Output in High Z (2)
5
6
7
8
10
15
Notes:
1 ) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5%. Commercial Only-Preliminary Data.
QUALITY SEMICONDUCTOR
2-17
QS8769
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
■10(3)
-12 (3)
-15
-20
-25
15
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
twc
Write Cycle Time
10
12
15
19
25
35
tew
Chip Select Valid to
tna oi wnie
9
_
10
_
13
L
17
20
_
30
_
tAW
Address Valid to
tna ot write
9
J.
10
_
13
_
17
20
_
30
_
t AS
Address
C n+ 1 i r\ 1 i m a
oeiup I ime
0
0
_
0
_
0
_
0
_
0
_ 1
tWP
Write Pulse width
9
I
10
12
-
16
20
30
-
tWR
Write
Recovery Time
0
0
0
0
0
0
tDW
Data Valid to
End of Write
6
7
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
4
5
6
7
8
12
tow
Output Active from
End of Write
2
2
2
2
2
3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
2-18
QUALITY SEMICONDUCTOR INC.
QS8769
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
tRC
C3
ADRS
X
ADDRESS VALID
t AA
DATA OUT
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
u* tRC (5) »
ADRS
DATA OUT
ADDRESS VALID
tACS
-« tLZ(4) r
X
'HZ (4)
TA VALID
Notes:
1 . WE"is high for Read cycle.
2. C3~is low for Read cycle #1 .
3. Address is valid prior to CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
QUALITY SEMICONDUCTOR INC.
2-19
QS8769
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
twc
WE
DATA OUT
DATA IN
I AW
t AS
tWP
tWZ(6)
<* *l
-an
tDW
tow
DATA VALID
l3
,•4
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,5 C5 controlled timing)
ADRS
C5
WE
DATA IN
twc
t AW
JAS_
_tcw_
tDW
tWR
4 »>
X
—
DATA VALID
Notes:
1 . WE or C5 must be high during address transitions.
2. A write occurs during the overlap of a tow and a tow WE
3. t WR is measured from the earlier of and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the tow transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
2-20
QUALITY SEMICONDUCTOR INC.
QS8780
Q
High-Speed CMOS
4Kx4 Cache Tag SRAM
with Reset
QS8780
ADVANCE
INFORMATION
FEATURES/BENEFITS
High Speed Match Access and Cycle times
MATCH output goes high on match
1 2ns/15ns/20ns/25ns/35ns Commercial
15ns/20ns/25ns/35ns/45ns Military
Low power, high-speed QCMOS™ technology
Single reset pulse clears all RAM data to zero
TTL level MATCH output
Available in 22-pin DIP, 24-pin ZIP,
& 24-pin 300 mil SOJ.
6-Transistor cell for high reliability
DESCRIPTION
The QS8780 is a high-speed 16K Cache Tag SRAM with reset. It is organized as a 4Kx4 SRAM with a
tag comparator between the data inputs and the RAM outputs. The match comparator output goes high
on a match and has full TTL output drive. The RAM may be reset with a single pulse, which sets all bits of
the RAM to logic zero. The fast address to match and data to match times provided by the 8780 allow
design of high speed cache memory systems required for fast CISC and RISC processors. The reset
feature allows fast cache flushing for task switching and logical cache designs. The 8780 is
manufactured in a high-performance CMOS process, and it is based on a 6-transistor cell design for high
reliability of data retention. Excellent latch-up and ESD protection are also provided.
FUNCTIONAL BLOCK DIAGRAM
Address
CTR
16,384 BIT
MEMORY
ARRAY
Write
WE
0~E —
I
Read
I/O
Read/Write Data I/O
Equal Mi
-
QUALITY SEMICONDUCTOR INC.
2-21
QS8780
PIN CONFIGURATIONS
AO C 1
A1 C 2
A2 C 3
A3 C 4
M C 5 1 18 □ A8
A5 C 6 Q 17 □ CCR
A6 C 7 16 □ I/O 4
A7 C 8 15 □ |/o 3
OE C 9 14 □ I/O 2
WE C 10 13 □ |/o 1
GND C 11 12 □ MATCH
22 □ Vcc
21 □ A11
20 □ A10
19 □ A9
; ig. :
ALL PINS TOP VIEW
PIN DESCRIPTION
Pin Name
I/O
Function
A
I
Address
I/O 1-4
I/O
Data
CUE
I
RAM Reset/Clear
WE
I
Write Enable
0~E
I
Output Enable
MATCH
0
Comparator Output
FUNCTION TABLE
CUE
0~E
WE
I/O
RAM
MATCH
Function
L
X
X
High-Z
Low
X
Clear RAM to all low (zero)
H
H
H
Data In
= Data In
H
Match Compare Valid
H
H
H
Data In
* Data In
L
Match Compare Invalid
H
L
H
Data Out
Data Out
H
Read
H
X
L
Data In
Data In
H
Write
X = Don! Care for inputs, Undefined for MATCH output
SSSm
2-22
QUALITY SEMICONDUCTOR INC.
QS8780
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground
DC Output Voltage Vq -0.5V
DC Input Voltage V| -0.5V
AC Input Voltage (for a pulse width <20 ns)
DC Output Current Max. sink current/pin
DC Output Current Max. source current/pin
TBIAS Temperature Under Bias, COM
TSTG Storage Temperature, COM
TBIAS Temperature Under Bias, MIL
TSTG Storage Temperature, MIL
-0.5V to +7.0V
toVcc +0.5V
toVCc +0.5V
-3.0V
50 mA
30 mA
-65° to +125°C
-65° to +125°C
-65° to +135°C
-65° to +155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
■
Ta=+25°C,f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
pF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY SEMICONDUCTOR INC.
2-23
-
QS8780
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4mA,Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc = MIN
0.4
0.4
| Hi |
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
jiA
Ho
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
1. Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
■
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-10
-12
1 5
-20
-25/-35
Unit
c
M
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
f = 0
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
f=fMAX
145
165
135
155
125
145
120
140
110
130
2-24
QUALITY SEMICONDUCTOR INC.
QS8780
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Match Timing Diagrams.
Symbol
Parameter
(D
■12
(3)
-1
5
!0
-S
5
Min
Max
Min
Max
Min
Max
Min
Max
MATCH CYCLE
tAM
Address to
Match Time
j -
12
-
15
-
20
-
25
tHAM
Match Valid Hold
from Address
2
-
2
-
2
-
2
-
t DM
Data to
Match Time
7.2
9
12
15
t HDM
Match Valid Hold
from Data
1
1
1
1
tOM
OE high to Match
valid
12
15
20
25
tHOM
Match hold from OE
0
0
0
0
tWM
WE high to Match
valid
12
15
20
25
t HWM
Match hold from WE
0
0
0
0
CLEAR CYCLE
tCLRW
CLR Pulse Width
50
50
50
50
tCLRR
CLR Recovery Time
CLR High to WE Low
10
10
10
10
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
QUALITY SEMICONDUCTOR INC.
2-25
i
QS8780
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-12
(3)
-15
-20
-25
(D
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
t RC
Read Cycle Time
1 2
1 5
1 9
25
■
t AA
Address
1 2
1 5
19
25
Access Time
tOH
Output Hold from
2
2
3
3
Address Change
tOE
Output Enable to
6
6
8
10
Data Valid
tOLZ
Output Enable to
2
2
2
2
Output in Low Z (2)
tOHZ
Output Enable to
4
5
7
8
Output in High Z (2)
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
!
2-26
QUALITY SEMICONDUCTOR INC.
QS8780
Commercial TA - 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-12
(3)
-15
-20
-25
(D
Min
Max
Min
Max
Min
Max
Min
Max
WRITE
CYCLE
twc
Write Cycle Time
12
-
1 5
19
25
t AW
Address Valid to
End of Write
10
1 3
17
-
20
-
t AS
Address
Setup Time
0
-
0
0
-
0
-
tWP
Write Pulse width
10
-
1 2
16
-
20
-
tWR
Write
0
-
0
0
0
Recovery Time
tDW
Data Valid to
End of Write
7
-
3
10
13
t DH
Data Hold Time
0
0
0
0
twz
Write Enable to
Output in High Z (2)
5
6
7
8
tow
Output Active from
End of Write (2)
2
2
2
2
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
2-27
QS8780
TIMING WAVEFORMS - MATCH CYCLE (1)
tRC
ADRS
WE
o~e
DATA IN
ADDRESS VALID
tWM
tOM
DATAVA .ID
^ tDM ^
t AM
MATCH
X
t HWM
tHOM
^ tHAM ^
t HDM
Notes:
1. WE, OE are high for Match cycle.
■
TIMING WAVEFORMS - CLEAR CYCLE
tCLRW
WE |
tCLRR
w — 1
2-28
QUALITY SEMICONDUCTOR INC.
QS8780
TIMING WAVEFORMS - READ CYCLE NO. 1 (1)
tRC (3)
ADRS "
X
OE
DATA OUT
ADDRESS VALID
t AA
tOE
tOH
■ ■ ":o::::::':;-:":::::
IPC
tOHZ (2).
DATA VALID
Notes:
1 . WEis high for Read cycle.
2. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
3. All read timings are referenced from the last valid address to the first transitioning address.
TIMING WAVEFORMS-WRITE CYCLE (1)
ADRS
WE
DATA OUT
DATA IN
twc
tAW
t AS
tWP
tWZ(3)
* *1
(2)
tWR
->r* — ►
tDW
tow
DATA VALID
Notes:
1. WE must be high during address transitions.
2. During this period the I/O pins are in the output state and input signals must not be applied.
3. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
QUALITY SEMICONDUCTOR INC.
2-29
QS8780
2-30
QUALITY SEMICONDUCTOR INC.
QS8881, QS8882
Q
High-Speed CMOS
16Kx4 SRAM
with Separate I/O
QS8881
QS8882
FEATURES/BENEFITS
• High Speed Access and Cycle times
• 10ns/12ns/15ns/20ns/25ns Commercial
• 1 5ns/20ns/25ns/35ns Military
• TTL compatible I/O
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883, Class B
• 6-Transistor cell for high reliability
• Ideal for reliable.dense memory systems
• Available in 28-pin DIPs, 28-pin 300 mil
SOJ , 28-pin LCC
• Low Standby current
• JEDEC standard pinout
DESCRIPTION
The QS8881 and QS8882 are high-speed 64K SRAMs organized as 16Kx4 with separate read and
write data buses. In the 8881, the read data outputs follow the inputs during a write; in the 8882, the
outputs are disabled during a write. The 8881 and 8882 are manufactured in a high-performance
CMOS process, and they are based on a 6-transistor cell design for high reliability of data retention.
Their high-speed access times make them useful in cache data RAM, cache tag RAMs, high-speed
scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low operating power and
excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
Dl
65,536 BIT
MEMORY
ARRAY
Write
-»5>-H~^
Read
Read/Write Data I/O
Note:
WE is not connected to Output Enable Gate 2 in the 8881 .
WE is connected to Output Enable Gate 2 as shown in the 8882.
QUALITY SEMICONDUCTOR INC.
2-31
QS8881, QS8882
PIN CONFIGURATIONS
*
A3
n 4
26 □
r A12
A4
J_J 5
25 □
r ah
A5
□ 6
24 □
r aio
A6
□ 7
23 □
r A9
A7
D 8
LCC
22 □
r D4
A8
D 9
21 □
r D3
D1
20 □
r Y4
D2
D 11
19 IZ
r Y3
C5T
n 12
18C
r Y2
CO
-* m cd I-.
J
X. r~
J
x I — j
PIN DESCRIPTION
LU Q
Pin Name
I/O
Function
A
I
Address
•
D
I
Write Data In
Y
0
Read Data Out
I
Chip Select
WE
I
Write Enable
I
Output Enable
FUNCTION
TABLE
C32
WE
Y Outputs
Power
Function
8881
8882
H
X
X
HighZ
HighZ
Standby
Deselect
X
H
X
HighZ
HighZ
Standby
Deselect
L
L
H
Data Out
Data Out
Active
Read
L
L
L
Data In
HighZ
Active
Write
■
2-32
QUALITY SEMICONDUCTOR INC.
QS8881, QS8882
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to Vcc + 0.5V
DC Input Voltage V, -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V ,
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
TSTG StorageTemperature.COM -65°to+125°C
TBIAS Temperature Under Bias, MIL -65° to +135°C
TSTG StorageTemperature.MIL -65°to+155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Name
Cin
Cin
Cout
Cout
Description
Input Capacitance
Input Capacitance
Output Capacitance
Output Capacitance
Conditions
Vin = 0 V PDIP Pkg.
Vin = 0 V SOJ Pkg.
Vout = 0V PDIP Pkg
Vout = 0 V SOJ Pkg.
Typ
2.5
Capacitance is guaranteed by design but not tested
Max
Unit
PF
PF
PF
7 pF
—
QUALITY SEMICONDUCTOR INC.
2-33
QS8881, QS8882
=
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc = MIN
0.4
0.4
| III |
Input Leakage
Vcc = MAX,
Vin = GNDtoVcc
5
10
HA
| Ho |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes:
1. Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-10
-12
1 5
-20
-25/-35
Unit
c
M
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = 0
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
145
165
135
155
125
145
120
140
110
130
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS > Vih, f = f MAX
60
70
60
70
60
70
60
70
60
70
Isb1
Full Standby
Current, Vcc = MAX
Outputs open
CSs Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
15
20
2-34
QUALITY SEMICONDUCTOR INC.
=
QS8881, QS8882
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
I
Parameter
(1)
-10 (3)
-12 (3)
-15
-20
-25
-35
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
10
12
15
19
25
35
t AA
Address
Access Time
-
10
12
-
15
-
19
-
25
-
35
t ACS
Chip Select
10
12
15
19
25
35
Access Time
tOH
Output Hold from
Address Change
2
2
2
3
3
3
tCLZ
Chip Select to
Output in Low Z (2)
2
2
2
2
2
3
tCHZ
Chip Select to
5
5
7
8
1 0
15
Output in High Z (2)
tOE
Output Enable to
Data Valid
5
6
6
8
10
18
tOLZ
Output Enable to
2
2
2
2
2
3
Output in Low Z (2)
tOHZ
Output Enable to
Output in High Z (2)
4
4
5
7
8
15
tPU
Chip Select to
Power Up Time (2)
0
0
0
0
0
0
tPD
Chip Select to
Power Down Time (2)
10
12
15
19
25
35
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
I
QUALITY SEMICONDUCTOR INC.
2-35
QS8881, QS8882
=
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(D
-10 (3)
-12 (3)
-15
-20
-25
-35
Min
Min
Min
Min
Max
Min
Max
Max
Mm
Max
Max
Max
WRITE CYCLE
twc
Write Cycle Time
10
-
12
-
15
-
19
-
25
-
35
-
tew
Chip Select Valid to
End of Write
8
-
10
-
13
-
17
-
20
-
30
-
tAW
Address Valid to
End of Write
8
-
10
-
13
-
17
-
20
-
30
-
t AS
Address
Setup Time
0
-
0
-
0
-;
0
-
0
-
0
-
tWP
Write Pulse width
8
-
10
-
1!
>
-
16
-
20
-
30
-
tWR
Write
necovery i ime
0
-
0
-
0
-
0
-
0
-
0
-
tDW
Data Valid to
hna oT write
5
-
6
-
8
-
10
-
13
-
18
-
t DH
Data Hold Time
0
0
0
0
0
0
twz
Write Enable to
Output in Hi Z (2,4)
4
5
6
7
8
12
tow
Output Active from
End of Write (4)(2)
2
2
2
2
2
3
tlY
Data to Output
Delay (5)
8
10
12
15
20
25
tWY
Write Enable to
Output Delay (5)
8
10
12
15
20
25
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commerciall Only-Preliminary Data
4) 8882 Only. (8881 outputs remain on during write.)
5) 8881 Only. (8882 outputs go to Hi-Z during write.)
2-36
QUALITY SEMICONDUCTOR INC.
QS8881, QS8882
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2,6)
C5 (6)
ADRS
DATA OUT
X
tRC (5)
ADDRESS VALID
t AA
tOH
X
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3,6)
ADRS
C5 (6)
OE
DATA OUT
Vcc SUPPLY Ice
CURRENT |sb
tRC (5)
ADDRESS VALID
t ACS
tOE
« l0LZ»,
« 1CLZ »
tPU
jr.
vc
x:
tOHZ(4).
t CHZ (4) ■
DATA VALID
tPD
Notes:
1 . WE~is high for Read cycle.
2. C~51s bw for Read cycle #1 .
3. Address is valid to or coincident with C~5 transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
6. CS is defined as active during the overlap of C5T and CS2. Both C5T and CSTmust be active for read or write.
QUALITY SEMICONDUCTOR INC.
2-37
QS8881, QS8882
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3,6 WE controlled timing)
ADRS
CS
WE
DATA OUT
twc
tAW
tWR
X
_
t AS
tWZ(5)
— <
tWP
(W$ start)
M —
tWY(7)
8882
8881
7~
DATA IN
tlY(7)
tDW
tow
tPH
DATA VALID
Notes:
1 . WE or CS must be high during address transitions.
2. A write occurs during the overlap of a tow CS and a low WE.
3. t WR is measured from the earlier of CS and WE going high to end of the write cycle.
4. If the CS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
5. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
6. CS is defined as active during the overlap of CST and CSS. Both CS1 and CS2must be active for read or write.
7. t WY and t IY are data in to data out flow through times during write and are defined for 8881 only.
* •-
QUALITY SEMICONDUCTOR INC.
QS8881, QS8882
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,4,6 ZS controlled timing)
twc
ADRS
US
WE
DATA OUT
DATA IN
Notes:
1 . WE or must be high during address transitions.
2. A write occurs during the overlap of a tow and a low WE.
3. t WR is measured from the earlier of and WE going high to end of the write cycle.
4. tf the JTS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
5. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
6. ?T5 is defined as active during the overlap of CS1 and CS2. Both CS1 and C52~must be active for read or write.
7. t WY and t IY are data in to data out flow through times during write and are defined for 8881 only.
QUALITY SEMICONDUCTOR INC.
2-39
QS8881, QS8882
■
■
QUALITY SEMICONDUCTOR INC.
QS8883
Q
High-Speed CMOS
16Kx4 Cache Tag SRAM
QS8883
FEATURES/BENEFITS
High Speed Match Access and Cycle times
10ns, 12ns/15ns/20ns/25ns/35ns Commercial
15ns/20ns/25ns/35ns/45ns Military
TTL compatible I/O
Low power, high-speed QCMOS® technology
MATCH output goes high on match
TTL level MATCH output
Available in 24-pin DIPs, 24-pin ZIP
24-pin 300 mil, SOJ , 28-pin LCC, QSOP
6-Transistor cell for high reliability
DESCRIPTION
The QS8883 is a high-speed 64K Cache Tag SRAM organized as a 1 6Kx4 SRAM with a tag comparator
between the data inputs and the RAM sense amplifier outputs. The match comparator output goes high
on a match and has full TTL output drive. The fast address to match and data to match times provided by
the 8883 allow design of high speed cache memory systems required for fast CISC and RISC
processors. The 8883 is manufactured in a high-performance CMOS process, and it is based on a 6-
transistor cell design for high reliability of data retention. Low operating power and excellent latch-up
and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
65,536 BIT
MEMORY
ADDI
DEC
ARRAY
■
MATCH
■
2-41
=
QS8883
PIN CONFIGURATIONS
AO
c
1
24
□ Vcc
A1
A2
c
2
23
□ A13
r
i —
Q
o
Q.
O
OO
C.C.
A3
C
4
(0
21
□ A11
A4
c
5
o
20
□ A10
A5
c
6
-J
19
□ A9
A6
c
7
o
(0
18
□ MATCH
A7
c
8
17
□ I/O 4
A8
c
9
qT
16
□ I/O 3
cs
c
10
5
15
□ I/O 2
0~E
c
11
14
□ 1/01
GND
c
12
13
1
□ WE
INDE>
ALL PINS TOP VIEW
»- co m
< < < <
Q i- co
§ § 2
X
o
2
1.
A1 J
□ 4
A2 "]
□ 5
A3 1
□ 6
A4 J
□ 7
A5 H
□ 8
A6 5
■
□ 9
A7 1
□ 10
A8 I
□ 11
cs h
□ 12
LCC
26 □
NC
25 □
A13
24 □
A12
23 □
A11
22 □
A10
21 □
A9
20 □
I/O 4
19D
I/O 3
18D
I/O 2
CO
2 5! 8
< < >
CM ■* JO 00 O CM
CD
T—
S 8
CM
CM
CM
zfp
co in r*. o
CO
LO
CM
CO
CM
O CM CO CO
< < < < < lu
lo
WE <
102 (
o <
A11 C
A13 C
eggs
PIN DESCRIPTION
Pin Name
I/O
Function
A
I
Address
I/O 1-4
I/O
Data
CS
I
Chip Select
WE
I
Write Enable
0~E
I
Output Enable
MATCH
o
Comparator Output
FUNCTION TABLE
C5
WE
OE
I/O
RAM
MATCH
Power
Function
H
X
X
HighZ
HighZ
H
Standby
Deselect
L
H
H
Data In
= Data In
H
Active
Match Compare Valid
L
H
H
Data In
# Data In
L
Active
Match Compare Invalid
L
H
L
Data Out
Data Out
H
Active
Read
L
L
X
Data In
Data In
H
Active
Write
X = Don't Care for inputs
QS8883
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to Vcc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
TSTG StorageTemperature.COM -65°to+125°C
TBIAS Temperature Under Bias, MIL -65°to+135°C
TSTG Storage Temperature, MIL -65° to +155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
pF
Cout
Output Capacitance
Vout = 0VPDIPPkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
j
QUALITY SEMICONDUCTOR INC.
2-43
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4mA,Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA, Vcc = MIN
0.4
0.4
III
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
HA
| lb |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-10
-12
-15
-20
-25
Unit
c
M
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
CS < Vil, f = 0
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = f MAX
145
165
135
155
125
145
120
140
115
135
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS>Vih, f= f MAX
60
70
60
70
60
70
60
70
60
70
Isb1
Full Standby
Current, Vcc = MAX
Outputs open
CS > Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
15
20
-
2-44
QUALITY SEMICONDUCTOR INC.
=
QS8883
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-10(3)
12 (3)
■15
-20
-25
(D
Min
Max
Min | Max
Min
Max
Min
Max
Min | Max
MATCH CYCLE
t AM
Address to
Match Time
-
10
12
-
15
-
20
-
25
tHAM
Match Valid Hold
from Address
2
-
j
-
3
-
3
-
3
-
t DM
Data to
Match Time
-
6
7.2
-
9
-
12
-
15
t HDM
Match Valid Hold
from Data
1
-
1
-
1
-
1
-
1
-
tCM
Chip Select to
MATCH Valid
10
12
15
20
25
tHCM
Match Valid Hold
from Chip Select
2
2
2
2
2
tOM
OE High to
Match Valid
8
10
12
15
20
tHOM
Match Valid Hold
from Output Enable
0
0
0
0
0
tWM
WE High to
Match Valid
10
12
15
20
25
tHWM
Match Valid Hold
from Write Enable
0
C
0
0
0
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
QUALITY SEMICONDUCTOR INC.
QS8883
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-10 (3)
-12 (3)
-15
-20
-25
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
10
-
12
-
15
-
19
-
25
-
t AA
Address
_
10
_
12
_
15
_
19
_
25
Access Time
t ACS
Chip Select
_
10
_
12
_
15
_
19
_
25
Access Time
tOH
Output Hold from
2
_
2
_
2
3
3
Address Change
tCLZ
Chip Select to
vJLapUt in LOW 4- \d)
2
-
2
-
2
-
2
-
2
-
tCHZ
Chip Select to
.
4
-
5
.
7
-
8
-
10
Outnut in Hinh 7 19\
V/UIL/UL III 1 HUM i— \C- 1
tOE
Output Enable to
Data Valid
5
6
6
8
10
tOLZ
Output Enable to
Output in Low Z (2)
2
2
2
2
2
tOHZ
Output Enable to
Output in High Z (2)
4
4
5
7
8
tPU
Chip Select to
0
0
0
0
0
Power Up Time (2)
tPD
Chip Select to
Power Down Time (2)
10
12
15
19
25
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only.
2-46
=
QUALITY SEMICONDUCTOR INC.
QS8883
—
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(1)
-10 (3)
-12 (3)
-15
-20
-25
Min
Max
Min
Max
Min
Min
Max
Min
Max
WRITE CYCLE
twc
Write Cycle Time
10
-
12
-
15
-
19
-
25
-
tew
Chip Select Valid to
End of Write
:
8
-
10
-
13
-
17
-
20
-
tAW
Address Valid to
End of Write
8
-
10
-
13
-
17
-
20
-
t AS
Address
Setup Time
0
-
0
-
0
-
0
-
0
-
tWP
Write Pulse width
-
10
-
12
-
16
-
20
-
tWR
Write
Recovery Time
0
0
0
0
0
tDW
Data Valid to
End of Write
6
8
10
13
tDH
Data Hold Time
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
5
6
7
8
tow
Output Active from
End of Write (2)
2
2
2
2
Notes:
1 ) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% for Commercial Only-Preliminary Data
QUALITY SEMICONDUCTOR INC.
QS8883
TIMING WAVEFORMS - MATCH CYCLE (1)
tRC
ADRS
WE
DATA IN
MATCH
pa
ADDRESS VALID
tCM
tWM
tOM
DATA VALID
« tDM ►
t AM
111 si
X
t HCM
t HWM
^ t HOM ^
^ tHAM ^
t HDM
1 . WET5E"are high for Match cycle.
L
■
2-48
QS8883
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
M tRC (5) f
ADRS
DATA OUT
X
ADDRESS VALID
X
t AA
tOH
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
t RC (5)
ADRS
C5
0~E
DATA OUT
ADDRESS VALID
t ACS
««_LOLZ>
1
t OHZ (4) ,
^ 1CHZ(4)^
DATA VALID
I
tPU
tPD
Vcc SUPPLY Ice .
CURRENT |sfc) >
Notes:
1 . WE~is high for Read cycle.
2. CSIs low for Read cycle #1 .
3. Address is valid to or coincident with CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage
5. All read timings are referenced from the last valid address to the first transitioning
i
QUALITY SEMICONDUCTOR INC.
2-49
QS8883
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
twc ^
WE
DATA OUT
DATA IN
tAW
tWR
4 tAS »
twp
tWZ(6)
< *1
tDW
tow
DATA VALID
TIMING WAVEFORM
No. 2 (1,2,3,5 C5 controlled timing)
ADRS
DATA IN
DATA VALID
1
Notes:
1 . WE or C3J must be high during address transitions.
2. A write occurs during the overlap of a low C3 and a low WE
3. t WR is measured from the earlier of CS and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
2-50
QUALITY SEMICONDUCTOR INC.
QS8885, QS8886
Q
High-Speed CMOS
16Kx4 SRAM
with Output Enable
QS8885
QS8886
High Speed Access and Cycle times
8ns/1 Ons/1 2ns/1 5ns/20ns/25ns Commercial
1 2ns/1 5ns/20ns/25ns/35ns Military
TTL compatible I/O
Low power, high-speed QCMOS™ technology
Military product compliant to MIL-STD-883, Class B
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
Available in 24-pin DIPs, 24-pin ZIP,
24-pin 300 mil SOJ, 28-pin LCC & QSOP
Low Standby current
JEDEC standard pinout
DESCRIPTION
The QS8885 and QS8886 are high-speed 64K SRAMs organized as 16Kx4. The 8885 has two chip
selects, and both have output enable. The 8885 and 8886 are manufactured in a high-performance
CMOS process, and they are based on a 6-transistor cell design for high reliability of data retention.
Their high-speed access times make them useful in cache data RAM, cache tag RAMs, high-speed
scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low operating power and
excellent latch-up and ESD protection are provided.
^======
FUNCTIONAL BLOCK DIAGRAM
Address ■
(8885 Only) CSS
WE •
65,536 BIT
MEMORY
ARRAY
rT3>
Write
OE
I/O
Read
ReaoVWrite Data I/O
=
QUALITY SEMICONDUCTOR INC.
2-51
QS8885, QS8886
PIN CONFIGURATIONS
AO
A1
A2
A3
A4
A5
A6
A7
A8
C5/C5T
0~E
GND
1
24
□ Vcc
2
23
□ A13
3
Q.
o
22
□ A12
4
W
21
□ A11
5
o
20
□ A10
6
19
□ A9
o
□ RC/C52
7
CO
18
8
17
□ I/O 4
9
qT
16
□ I/O 3
10
o
15
□ I/O 2
11
14
□ 1/01
12
13
□ WE
oo
oo
co
loo
K->
&
INDEX.
o
<
CO
A1 T
3 4
A2 T
3 5
A3 T
H 6
A4 T
3 7
A5 T
D 8
A6 T
A7 7
3 10
A8 T
H 11
CS~/C~S7 7
3 12
\
CO
(8886)
LU
D
Q t- co icm
^-i-O'-comr^looZOOW
<<><<<<KJC3^:=!0
r^i r\ r\ r\
<D CO O CM ■*
t- t- CM CM CM
ZIP
r- n io
cTi i — n
f-COWh~Cr>,-,-,-,-,-CMCM
O i- CO O CM
<'-'-<<<
< <
<° co HI hi cm
< < b S 9 9
o
o o o
z > z
LCC
Q
Note:
Pin 10 of DIP/SOIC/ZIP and pin 12 of LCC
is CS for 8886, CS1 for 8885
Pin 18 of DIP/SOIC/ZIP and pin 15 of LCC
is NC for 8886, CS2for 8885
PIN DESCRIPTION FUNCTION TABLE
Pin Name
I/O
Function
C5T
C55
WE
I/O
Power
Function
A
I
Address
H
X
X
HighZ
Standby
Deselect
1/01-4
I/O
Data
X
H
X
HighZ
Standby
Deselect
CS7C37/2
I
Chip Select
L
L
H
Data Out
Active
Read
WE
I
Write Enable
L
L
L
Data In
Active
Write
0"E
I
Output Enable
2-52
QUALITY SEMICONDUCTOR INC.
QS8885, QS8886
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to Vcc + 0.5V DC
Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65°to+125<>C
TSTG StorageTemperature.COM -65°to+125°C
TBIAS Temperature Under Bias, MIL -65°to+135°C
TSTG StorageTemperature.MIL -65°to+155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta-+25°C,f-1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
pF
Cout
Output Capacitance
Vout = 0V PDIP Pkg.
7
pF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
-
=
QUALITY SEMICONDUCTOR INC.
2-53
QS8885, QS8886
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test conditions
Commercial
Military
Unit
Min
Max
Min
Max
\/ih
vin
input nlon voltage
Logic nign tor mii inputs
2.2
6.0
2.2
6.0
\/rilte
VOIIS
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8 mA, Vcc = MIN
0.4
0.4
|i|
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
uA
1 Bo |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-8
-10
-12
1 5
-20
-25/-35
Unit
C
C
c
M
M
C
M
C
M
C
M
led
Static Operating
Current, Vcc = MAX
Outputs open
CS^Vil, f = 0
110
100
120
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
160
145
165
135
155
125
145
120
140
110
130
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS 2 Vih, f = f MAX
70
60
70
60
70
60
70
60
70
60
70
Isbl
Full Standby
Current, Vcc = MAX
Outputs open
CSsrVhc, f = 0
Vin < Vic or Vin >
Vhn
20
15
20
15
20
15
20
15
20
15
20
2-54
QUALITY SEMICONDUCTOR INC.
QS8885, QS8886
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-8(3)
-10(3)
12
15
20
25
35
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
8
10
12
15
19
25
35
t A A
Address
Access Time
o
0
m
1U
1 0
1 c.
1 0
t-0
t ACb
Chip Select
Access Time
"
o
o
"
10
"
1 i
"
1o
"
19
"
"
oo
tOH
Output Hold
fromAddress
Change
1.5
2
2
2
3
3
3
tCLZ
Chip Select to
WUlfJUL III LUW L.
(2)
1.5
2
2
2
2
2
3
tCHZ
Chip Select to
Output in High Z
(2)
4
4
5
7
8
10
15
tOE
Output Enable
toData Valid (2)
4
5
6
6
8
10
18
tOLZ
Output Enable to
Output in Low Z
(2)
1.5
2
2
2
2
2
3
tOHZ
Output Enable to
Output in High Z
4
4
4
5
7
8
15
(2)
tPU
Chip Select to
Power Up Time (2)
0
0
0
0
0
0
0
tPD
Chip Select to
Power Down Time
(2)
8
10
12
15
19
25
35
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data.
QUALITY SEMICONDUCTOR INC.
2-55
QS8885, QS8886
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
■8(3)
-10
(3)
-12
-15
-20
-25
-35
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE
CYCLE
twc
Write Cycle Time
8
10
-
12
15
19
25
35
tew
Chip Select Valid to
End of Write
7
8
-
10
13
17
20
30
tAW
Address Valid to
7
8
10
_
13
17
20
30
tAS
Address
Setup Time
0
0
0
0
0
0
0
tWP
Write Pulse width
7
8
-
10
12
16
20
30
tWR
Write
Recovery Time
0
0
•
0
0
0
0
0
tDW
Data Valid to
End of Write
4
5
6
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
4
4
5
6
7
8
12
tow
Output Active from
End of Write
1.5
2
2
2
2
2
3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data .
2-56
QUALITY SEMICONDUCTOR INC.
QS8885, QS8886
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2,6)
tRC
C5 (6)
ADRS
DATA OUT
TIMIN
■
J2_
—
X
ADDRESS VALID
— v
t AA
3c
r :
DATA VALID
RMS - READ CYCLE NO. 2 (1,3,6)
t RC (5) .
ADRS
C5 (6)
OE (6)
DATA OUT
ADDRESS VALID
S
tACS
«t0LZ»
« tCLZ »
X
t OHZ (4) ,
t CHZ (4)
DATA VALID
^ tPU
*
tPD
Vcc SUPPLY Ice
CURRENT |sb
Notes:
■
1 . WE~is high for Read cycle.
2. 8886 CS"is low for Read cycle #1 . Both CST and CSS are low for 8885.
3. Address is valid to or coincident with CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
6. CS applies to CS on the 8886 and the combination of CST and CSS on the 8885.
QUALITY SEMICONDUCTOR INC.
2-57
QS8885, QS8886
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
* ^£ *
ADRS "
C5
WE
DATA OUT
DATA IN
tAW
t AS
tWP
y
tWZ(6)
+ tDW.
T
tWR
< ►
tow
< ►
—
DATA VALID
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,5 C5 controlled timing)
ADRS
WE
twc
DATA IN
t AW
JAS_
1CW
-
y
-4c
tDW
tWR
4 ►
DATA VALID
Notes:
1 . WE or CS must be high during address transitions.
2. A write occurs during the overlap of a low CS and a low WE
3. t WR is measured from the earlier of CS and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
2-58
QUALITY SEMICONDUCTOR INC.
QS8888
Q
High-Speed CMOS
16Kx4 SRAM
with Common I/O
QS8888
FEATURES/BENEFITS
• High Speed Access and Cycle times
• 8ns/10ns/12ns/15ns/20ns/25ns Commercial
• 12ns/15ns/20ns/25ns/35ns Military
• TTL compatible I/O
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883, Class B
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
Available in 22-pin DIPs, 24-pin ZIP,
24-pin 300 mil SOJ , 22-pin LCC, QSOP
Low Standby current
JEDEC standard pinout
DESCRIPTION
The QS8888 is a high-speed 64K SRAM organized as 16Kx4 . It is manufactured in a high-performance
CMOS process, and it based on a 6-transistor cell design for high reliability of data retention. The high-
speed access times of the QS8888 make it useful in cache data RAM, cache tag RAMs, high-speed
scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low operating power and
excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
C5
65,536 BIT
MEMORY
ARRAY
WE
Data
r— ^ write
j^_J n i i Read
| Read/Write Data I/O -»{^>-
QUALITY SEMICONDUCTOR INC.
2-59
—
PIN CONFIGURATIONS
QS8888
c
c
c
c
c
c
c
c
c
gndC
AO
A1
A2
A3
A4
A5
A6
A7
A8
C5
1
2
3
4
5
6
7
8
9
10
11
0.
Q
22
21
20
19
18
17
16
15
14
13
12
□ VCC
□ A13
^ A12
□ A11
□ A10
□ A9
□ I/O 4
^ I/O 3
J I/O 2
D 1/01
□ WE
ALL PINS TOP VIEW
PIN DESCF
IIPTION
Pin Name
I/O
Function
A
I
Address
1/01 - 1/04
I/O
Data
C5
I
Chip Select
WE
I
Write Enable
FUNCTION TABLE
C3
WE
I/O
Power
Function
H
X
HighZ
Standby
Deselect
L
H
Data Out
Active
Read
L
L
Data In
Active
Write
2-60
QUALITY SEMICONDUCTOR INC.
QS8888
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to V<x + 0-5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage {for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65°to+125°C
TSTG StorageTemperature.COM -65°to+125°C
TBIAS Temperature Under Bias, MIL -65° to +135°C
TSTG StorageTemperature.MIL -65°to+155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
pF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0 V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY SEMICONDUCTOR INC.
2-61
QS8888
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc = MIN
0.4
0.4
| III |
Input Leakage
VCC = MAX,
Vin = GND to Vcc
5
10
HA
| HO |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes:
1. Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-8
-10
■12
1 5
-20
-25/-35
Unit
C
c
M
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = 0
110
100
120
100
120
100
120
100
120
100
120
mA
Icc2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
160
145
165
135
155
125
145
120
140
110
130
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS>Vih, f= f MAX
70
60
70
60
70
60
70
60
70
60
70
Isb1
Full Standby
Current, Vcc = MAX
Outputs open
CS>Vhc, f = 0
Vin < Vic or Vin > Vhc
20
15
20
15
20
15
20
15
20
15
20
2-62
QS8888
^ ^— ^— ^ — <—
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-8(3)
-10(3)
-12 (3)
-15
-20
-25
-35
(1)
Min | Max
Min Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
8
10
12
15
19
25
35
t AA
Address
8
10
12
15
19
25
35
Access Time
t ACS
Chip Select
Access Time
8
10
12
15
19
25
35
tOH
Output Hold from
Address Change
1.5
2
2
2
3
3
3
tLZ
Chip Select to
Output in Low Z (2)
1.5
2
2
2
2
2
3
tHZ
Chip Select to
Output in High Z (2)
4
5
5
7
8
10
15
tPU
Chip Select to
Power Up Time (2)
0
0
0
0
0
0
0
tPD
Chip Select to
Power Down Time (2)
8
10
12
15
19
25
35
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested
2) This parameter is guaranteed by design but not tested.
3) ForVcc±5%. Commercial Only-Preliminary Data.
QUALITY SEMICONDUCTOR INC.
2-63
Ck S 8888
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(1)
8(3)
-10(3)
-12
-15
-20
-25
-35
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
t WO
\A/r rto Time*
vvrne oycie i ime
Q
O
i U
1 9
1 £
10.
t OW
Unip beiect Valid
to End of Write
7
Q
O
1 n
■I 7
ou
4 A \ A/
t AW
« _i _i w_i:_i
Address Valid to
End of Write
-7
1
o
o
1 0
1 J
1 /
on
ou
t AS
Address
Setup Time
0
0
0
0
0
0
0
t Wr
\A/rita Pi ilea
vvme ruise
width
o
o
i n
1 0
1 b
ou
tWR
Write Recovery
Time
0
0
0
0
0
0
0
tDW
Data Valid to
End of Write
4
5
6
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
4
4
5
6
7
8
12
tow
Output Active
from End of Write
(2)
1.5
2
2
2
2
2
3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
2-64
QUALITY SEMICONDUCTOR INC.
QS8888
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
tRC (5)
ADRS
DATA OUT
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
tRC (5)
ADRS
DATA OUT
Vcc SUPPLY Ice
CURRENT ,„u
— '
ADDRESS VALID
X
« tHZ(4)»
DATA VALID
tPU
tPD
....
Js-_
Notes:
1 . WE~is high for Read cycle.
2. " CSTis low for Read cycle #1 .
3. Address is valid to or coincident with CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
■
QUALITY SEMICONDUCTOR INC.
QS8888
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
ADRS
WE
DATA OUT
DATA IN
_1WS
tAW
t AS
tWP
tWZ(6)
+ *l
—
tDW
tow
DATA VALID >
TIMING WAVEFORM
ADRS "
C5
WE
DATA IN
Notes:
1 . WE or must be high during address transitions.
2. A write occurs during the overlap of a low C5 and a low WE
3. t WR is measured from the earlier of C5 and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applie
5. If the C5 low transition occurs simultaneously with or after the WE low transition, the outp
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
QUALITY SEMICONDUCTOR INC.
i
QS88180, QS88160
Q
High-Speed CMOS
Dual 4Kx16/18 SRAM
with Latched Addresses
WO
QS88160
Preliminary
FEATURES/BENEFITS
Dual 4Kx18/1 6 allows 2-way set associative cache
Byte enables for byte/word read/write
20ns/25 ns/30ns/35 ns Taa commercial
25 ns/30ns/35/45 ns Taa military
Military product compliant to MIL-STD-883, Class B
=
386/486 compatible
6-Transistor cell tor high reliability
Low power, high-speed QCMOS™ technology
Available in 52-pin PLCC
DESCRIPTION
The 88180 is a high performance CMOS SRAM with a capacity of 144K bits organized as two banks of
4K words x 18 bits with a common address latch. The 88160 is a 16-bit version of the 88180. These
parts can be used effectively in 2-way set associative caches such as with the 82385 Cache Controller
for the 80386. The 88180 and 88160 leave A12 unlatched to provide high speed odd/even word
access for two word lines as used by 82385 cache controllers in the 64K byte mode.. The 88180/88160
are manufactured with state-of-the-art QCMOS™ processing technology. They are assembled in a 52-
pin PLCC and require a single 5 V power supply .
FUNCTIONAL BLOCK DIAGRAM
_
C50
C5T -
4Kx8/9
SRAM
0-7, DP0
Bank A
4K x 8/9
SRAM
8-15, DP1
Bank A
D0-D15
' DP0, DP1
4KX8/9
4KX8/9
SRAM
SRAM
0-7, DP0
8-15, DP1
Bank B
Bank B
QUALITY SEMICONDUCTOR INC.
2-67
QS88180, QS88160
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Name
I/O
Function
Pin Name
I/O
i 1
Function
AO-12
I
Address
WEA,"WEB
I
Write Enable, Bank A, B
DO-7, D8-15
I/O
Read/Write Data, Byte 0, 1
OEAVOEB
I
Output Enable, Bank A, B
DPO, DP1
I/O
Read/Write Parity, Byte 0, 1
(8818, 8819 only)
CALEN
I
Address Latch Enable
MODE
I
Mode Control
CE
I
Global Chip Enable
I
Chip Select Byte 0, 1
2-68 QUALITY SEMICONDUCTOR INC.
QS88180, QS88160
FUNCTION TABLE
OPERATION
CONTROL SIGNALS
Dual 4K Mode: MODE = H
DATA BUS
CE
C50
C3T
OEA
OEB
WES
WEB
DO-7, DPO
D8-15, DP1
Chip Disabled
H
X
X
X
X
X
X
Hi-Z
Hi-Z
Bytes Disabled
X
H
H
X
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
X
X
X
H
H
X
X
Hi-Z
Hi-Z
Outputs Disabled
X
X
X
L
L
X
X
Hi-Z
Hi-Z
Read DO-7, DPO Bank A
L
L
H
L
H
H
H
Data Out
Hi-Z
Read DO-7, DPO Bank B
L
L
H
H
L
H
H
Data Out
Hi-Z
Read D8-15, DP1 Bank A
L
H
L
L
H
H
H
Hi-Z
Data Out
Read D8-15, DP1 BankB
L
H
L
H
L
H
H
Hi-Z
Data Out
ReadDO-15, DPO Bank A
L
L
L
L
H
H
H
Data Out
Data Out
Read DO-15, DPO Bank B
L
L
L
H
L
H
H
Data Out
Data Out
Write DO-7, DPO Bank A
L
L
H
X
X
L
H
Data In
Hi-Z
Write DO-7, DPO Bank B
L
L
H
X
X
H
L
Data In
Hi-Z
Write D8-15, DP1 Bank A
L
H
L
X
X
L
H
Hi-Z
Data In
Write D8-15, DP1 BankB
L
H
L
X
X
H
L
Hi-Z
Data In
Write DO-15, DP1 Bank A
L
L
L
X
X
L
H
Data In
Data In
Write DO-15, DP1 BankB
L
L
L
X
X
H
L
Data In
Data In
Write DO-7 Banks A&B
L
L
H
X
X
L
L
Data In
Hi-Z
Write D8-15Banks A&B
L
H
L
X
X
L
L
Hi-Z
Data In
Write DO-15 Banks A&B
L
L
L
X
X
L
L
Data In
Data In
OPERATION
CONTROL SIGNALS
8KMode: MODE = L
DATA BUS
CE
C50
C5T
OEA
DEB
WES
WEB
DO-7, DPO
D8-15, DP1
Chip Disabled
H
X
X
X
X
X
X
Hi-Z
Hi-Z
Bytes Disabled
X
H
H
X
X
X
X
Hi-Z
Hi-Z
Outputs Disabled
X
X
X
H
H
X
X
Hi-Z
Hi-Z
Read DO-7, DPO
L
L
H
L
L
H
H
Data Out
Hi-Z
Read D8-15, DP1
L
H
L
L
L
H
H
Hi-Z
Data Out
Read DO-15, DPO.DP1
L
L
L
L
L
H
H
Data Out
Data Out
Write DO-7, DPO
L
L
H
X
X
L
L
Data In
Hi-Z
Write D8-15, DP1
L
H
L
X
X
L
L
Hi-Z
Data In
Write DO-15, DPO, DP1
L
L
L
X
X
L
L
Data In
Data In
QUALITY SEMICONDUCTOR INC.
2-69
QS88180, QS88160
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground
DC Output Voltage VQ -0.5V
DC Input Voltage V| -0.5V
AC Input Voltage (for a pulse width <20 ns)
DC Output Current Max. sink current/pin
DC Output Current Max. source current/pin
TBIAS Temperature Under Bias, COM
TSTG Storage Temperature, COM
TBIAS Temperature Under Bias, MIL
TSTG Storage Temperature, MIL
-0.5V to +7.0V
to VCC + 0.5V
to Vcc + 0.5V
-3.0V
50 mA
30 mA
-65° to +125°C
-65° to +125°C
-65° to +135°C
-65° to +155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V
7
PF
Cout
Output Capacitance
Vout = 0 V
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
2-70
QUALITY SEMICONDUCTOR INC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 125° C, Vcc = 5.0V+1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -1 mA,Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 4mA, Vcc = MIN
0.4
0.4
m
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
uA
| llo |
Output Leakage
Vcc = MAX,
5
10
Vout = GNDtoVcc
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-20
-25
Unit
-30
-35
Icc2
Standby Current,
Addresses Latched
COM
60
60
60
60
mA
Vcc - MAX, Outputs open
CE>Vih,CALEN<Vil, f = 0
MIL
Icc3
Dynamic Operating Current,
Addresses Unlatched
Vcc = MAX, Outputs open
CE<Vil,CALEN>Vih, f = 1/tRC
COM
240
230
230
225
MIL
INC.
2-71
QS88180, QS88160
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vex = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted.
Symbol
Parameter
Note
(D
20 ns
25 ns
30 ns
35 ns
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Address Latch Parameters
t ASL
Address Setup to Latch Low
4
4
4
6
ns
tAHL
Address Hold to Latch Low
5
5
5
5
ns
t CALEN
Latch Enable Pulse width
8
8
8
10
ns
Read Cycle Parameters
tRC
Read cycle time
20
25
30
35
ns
t AA
Address Access
4
20
25
30
35
ns
t A12A
A1 2 Address Access
15
17
20
25
ns
tcs
tCE
Chip Select Access
20
25
30
35
ns
tOE
Output Enable
8
10
12
14
ns
tOH
Output Hold from Addrs
3
3
3
3
ns
tOLZ
Output Enable to Low Z
2
2
2
2
2
ns
tLZ
Chip Enable to Low Z
2
3
3
3
3
ns
tOHZ
Output Disable to High Z
2
10
12
15
15
ns
tHZ
Chip Disable to High Z
2
15
17
17
25
ns
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) Preliminary Data (Commercial only)
4) Measured from address transition when CALEN high or from the low-to-high transition of CALEN.
QUALITY SEMICONDUCTOR INC.
QS88180, QS88160
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
Parameter
Note
(1)
20 ns
25 ns
30 ns
35 ns
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Parameters
twc
Write cycle time
20
25
30
35
ns
t AS
■
Address Setup
0
0
0
0
ns
t AW
Address valid to end of write
4
12
15
18
21
ns
t A12W
A12 valid to end of write
12
15
18
21
ns
tew
Chip Sel. valid to end of write
4
12
15
18
21
ns
tWP
Write pulse width
5
12
15
18
21
ns
tWR
Write recovery time
0
0
0
0
ns
tDW
Data valid to end of write
8
10
12
12
ns
t DH
Data hold time after write
0
0
0
0
ns
tWHZ
Write enable to output hi-Z
2,6
15
17
20
20
ns
tWLZ
Write disable to output low-Z
2,6
3
3
3
3
ns
Notes:
1 ) See Test Circuit and Waveforms. Minimums guaranteed but not t
2) This parameter is guaranteed by design but not tested.
3) Preliminary Data (Commercial only)
4) Measured from address transition when CALEN high or from the low-to-high transition of CALEN.
5) Write occurs during the overlap of WE,"CE, and C5. Measurements are made from this overlap.
6) If CE,"C5, and WE go low simultaneously, the output remains in the Hi-Z s
QUALITY SEMICONDUCTOR INC.
=
2-73
QS88180, QS88160
Read Timing Diagram
It:
CALEN
Address
A12
DO-15
DPO, DP1
X
t CALEN .
«_ tASL.
tRC
. t AHL
t A12
t AA, t CS, t CE
— —
.
tHZ
>0
tOH
jOE.tOLZ tOHZ
>
■
2-74
QUALITY SEMICONDUCTOR INC.
QS88180, QS88160
i
Write Cycle 1 Timing Diagram - WE Controlled Write
CALEN
Address
A12
WE
»(
twc
t CALEN .
tASL.
. t AHL
Valid Address
>i
A12W
tAS.
t AW, tCW
. tWP _
tWHZ
DO-15
DPO, DP1 11
A K_s
tWR
DH
tWLZ
Write Data
QUALITY SEMICONDUCTOR INC.
2-75
QS88180, QS88160
Write Cycle 2 Timing Diagram - CE Controlled Write
!
CALEN
Address
A12
WE
DO-15
DPO, DP1
X
twc
t CALEN
- tASL.wL— _tAHL
Valid Address
t A12W
t AW, t CW
t AS
tWP
tDW
7 —
tWR
DH
Valid Data
2-76
Q
FEATURES/BENEFITS
• 8Kx18with burst mode for secondary cache
• 1 clock initial access + 1 clock/word
• 40, 33, 25 MHz clock frequency
• Low power, high-speed QCMOS™technology
High-Speed CMOS
8Kx18 Burst Mode SRAM
with Address Counter
QS88181
ADVANCE
INFORMATION
Selectable Binary and 486 type address counter
Byte enables for byte/word read/write
6-Transistor cell for high reliability
Available in 52-pin PLCC
DESCRIPTION
The 88181 is a high performance CMOS SRAM with burst mode capability and a capacity of 144K bits
organized as 8K words x 18 bits. An address latch is provided for the upper 1 1 bits, and a 2-bit address
counter is provided for bits AO and A1 . The 2-bit address counter has two pin selectable counting
modes: binary and 486 compatible. The 88181 burst mode capability allows two clock first access
followed by one clock/word for up to three additional words. The binary/486 mode address counter
makes the 88181 particularly useful for caches for the 486 and other fast RISC and CISC uP's. The
88181 is manufactured with state-of-the-art QCMOS™ processing technology. It is assembled in a 52-
pin PLCC and requires a single 5V power supply .
FUNCTIONAL BLOCK DIAGRAM
8Kx9
8Kx9
►
SRAM
SRAM
DO-7, DPO
►
D8-15, DP1
I
C5T-
D0-D15,
DPO, DP1
QUALITY SEMICONDUCTOR INC.
2-77
QS88181
PIN CONFIGURATIONS
cm co w to O k ^ "5 <2
<<<<< <>\(j<<<<<
46 □
L A12
45 £
L CE
44 £
L GND
43 □
L D15
42 C
41 □
[ D13
40 C
r D12
39 C
r GND
38 □
H D11
37 C
L D10
36 C
H D9
35 C
L D8
34 r
L DP1
PIN DESCRIPTION
J
Pin Name
I/O
Function
AO-12
I
Address
DO-7, D8-15
I/O
Read/Write Data, Byte 0, 1
DPO, DP1
I/O
Read/Write Parity, Byte 0, 1
CE
I
Global Chip Enable
C30,~C5T
I
Chip Select Byte 0, 1
CLK
I
Clock
CST
MODE
VCC
VCC
Pin Name
I/O
Function
WE
I
Write Enable
0"E
I
Output Enable
CACE
I
Clocked Address
Latch Enable
MODE
I
Counter Mode Control
BER
I
Burst Counter Load
2-78
QUALITY SEMICONDUCTOR INC.
=
QS88182
Q
High-Speed CMOS
Dual 4Kx18
Cache Tag SRAM
QS88182
ADVANCE
INFORMATION
FEATURES/BENEFITS
Dual 4Kx18 allows 2-way set associative cache tag
MATCH lines per bank allow direct bank UE drive
MATCH enable controls MATCH outputs for speed
20ns/25 ns/30 ns Taa Commercial
25ns/30ns Taa military
Military product compliant to MIL-STD-883, Class B
• Independent tag comparator/bank
• Comptible with 88180 Cache Data SRAM
• HIT line provides ORed match output for control
• 6-Transistor cell for high reliability
• Low power, high-speed QCMOS™ technology
• Available in 52-pin PLCC
DESCRIPTION
The 88182 is a high performance CMOS Cache Tag SRAM with a capacity of 144K bits organized as two
banks of 4K words x 18 bits and designed for 2-way set associative caches. A comparator is provided
for each bank which makes the 88182 particularly useful in 2-way set associative caches. Two MATCH
outputs are provided, one for each bank. An ORed match output, HIT, is provided for control use. A
match enable input is provided which allows the match decision to be enabled at the start of the cycle
rather than add a gate delay in series with the match decision at the end of the cycle. An address latch is
also provided. The 88182 is manufactured with state-of-the-art QCMOS™ processing technology. It is
assembled in a 52-pin PLCC and requires a single 5V power supply .
FUNCTIONAL BL(
DIAGRAM
WES-
OES-
CE-
CALEN
A0-11 -»[ Latch
1
MODE
-C - <
S c
O CO
o
4Kx18
SRAM
DO-15, DPO-1
Bank A
Comp
Comp
4Kx 18
SRAM
DO-15, DPO-1
Bank B
MATCH
ENABLE
HIT
MATCHA"
D0-D15,
DPO, DP1
MATCHES
QUALITY SEMICONDUCTOR INC.
2-79
QS88182
PIN CONFIGURATIONS
inde:
t- w n * m
< < < < <
z
o Ui
<£> O <
< > o
o i-
I-- 00 O) w t-
< < < < <
D13
D12
PIN DESCRIPTION
Pin Name
I/O
Function
AO-12
I
Address
DO-7, D8-15
I/O
Read/Write Data
DPO, DP1
I/O
Read/Write Byte Parity
CE
I
Global Chip Enable
WEA,~WEB
I
Write Enable, Bank A, B
oea;oeb
I
Output Enable, Bank A, B
Pin Name
I/O
Function
CALEN
I
Address Latch Enable
MODE
I
Mode Control
MATCHA",
MATCHB
0
Match Output per bank
HIT
0
Composite Match: A+B
MATCFTER
I
Match Enable
2-80
QUALITY SEMICONDUCTOR INC.
QS83280
Q
High-Speed CMOS
32Kx8 SRAM
with Common I/O
QS83280
ADVANCE
INFORMATION
FEATURES/BENEFITS
=
=
Equal access and cycle times
12ns/15ns/20ns/25ns/30ns Commercial
JEDEC standard pinout
TTL compatible I/O
Available in 28-pin 300/600-mil DIP, SOJ, PLCC, LCC
6-Transistor cell for high reliability
1 5ns/20ns/25ns/30ns Military
Military product compliant to MIL-STD-883
Low power, high-speed QCMOS™ technology
DESCRIPTION
The QS83280 is a high-speed 256K SRAM organized as 32K words of 8 bits. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS83280 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
C5
WE
0"E
I/O
8g
262,144 BIT
MEMORY
ARRAY
Write
-»[j>-H~^
Read
Read/Write Data I/O
INC.
s
QS83280
SSSBBSSSSSB
PIN CONFIGURATIONS
AO
A1
A2
A3
A4
A5
A6
A7
A8
1/01
I/02
I/03
GNDC
4
5
6
o
OT
7
8
9
o
10
11
12
13
14
28
27
26
25
24
23
22
21
20
MAIR8 8xXS
□ VCC IN
□ WE
□ A14
□ A13
□ A12
□ A11
□ OE
□ A10
□ C5
18
17
16
15
19 □ I/08
□ I/07
□ I/06
□ I/05
□ I/04
U <
m cm
A3 h
□ 4
A4 |]
□ 5
A5 J
— | 6
A6 1
□ 7
A7 1
A8 1
□ 9
A9 h
□ 10
1/01 1
□ 11
1/02 J
□ 12
LCC
■ .-j ■
ALL PINS TOP VIEW
| I 1 I
■
PIN DESCRIPTION
FUNCTION TABLE
Pin Name
I/O
Function
A
I
Address
1/01 - 1/08
I/O
Data
C5
I
Chip Select
WE
I
Write Enable
UE
I
Output Enable
Function
C3
WE
0~E
I/O
Power
Deselect
H
X
X
HighZ
Standby
Read
L
H
L
Data out
Active
Write
L
L
X
Data In
Active
Output
Disable
L
H
H
HighZ
Active
QS83280
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to Vqc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
TSTG Storage Temperature, COM -65° to +125°C
Tbias Temperature Under Bias, MIL -65° to +135°C
TSTG Storage Temperature, MIL -65° to +155°C
.-' IKK
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C, f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0 V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
t
7
PF
-
c
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY SEMICONDUCTOR INC.
DC ELECTRICAL CHARACTERISTICS OVtH UHbHAHNU HANOC
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±10%
Qutnhnl
oyniuui
Paramotor
rdl al 1 1 c I c f
icai ^uiiuiiiuiid
Commercial
Military
Unit
Min
IVldA
Min
May
IVldA
Vih
VIII
Innirt Hlf^H Vnltanp
ii ifjui niun vuiiayc
I nnif Hinh fnr All Inniite
2.2
6.0
2.2
6.0
Volts
V5I
Input LOW Voltage (1)
Logic Low for All Inputs
n ft
n r
Voh
wuipui niun vuiiayc
loh - -4 mA Vnr - MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc = MIN
0.4
0.4
I HI
Input Leakage
Vcc = MAX,
vin = unu to vcc
5
10
uA
| lb |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
Chip deselcted
5
10
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-12
-15
-20
-25/-30
Unit
C
M
C
M
C
M
C
M
led
Static Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = 0
100
120
100
120
100
120
100
120
mA
Icc2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
180
190
170
180
160
170
150
160
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS>Vih, f= f MAX
90
100
90
100
90
100
90
100
Isb1
Full Standby Current,
Vcc = MAX
Outputs open
CS>Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
2-84
QS83280
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
12ns(3)
15ns(3)
20ns
25ns
30ns
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min| Max
READ CYCLE
tRC
Read Cycle Time
12
-
15
-
20
-
25
-
30
t AA
Address
-
12
-
15
-
20
-
25
-
30
Access Time
t ACS
Chip Select
-
12
-
15
-
20
-
25
-
30
ArPo« Timo
nouQgs i line
tOH
Output Hold from
2
-
2
-
2
-
2
-
2
n vj ui coo v 1 1 c* 1 1 y ~
tCLZ
Chip Select to
2
-
2
-
2
-
2
-
2
Output in Low Z (2)
tCHZ
Chip Select to
Output in High Z (2)
-
6
-
7
-
8
-
10
12
tOE
Output Enable
7
8
10
12
1 5
Access Time
tOHZ
Output enable to
6
7
8
10
12
output in High Z (2)
tOLZ
Output enable to
0
0
0
0
0
output in Low Z (2)
tPU
Chip select to
0
0
0
0
0
Power-Up time(2)
tPD
Chip select to
Power-Down time
12
15
20
25
30
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
=
QUALITY SEMICONDUCTOR INC.
Commercial TA = 0° C to 70°C, Vcc = 5.0V+10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(D
12ns (3)
Min Max
-15ns(3)
Min I Max
-20ns
Min Max
-25ns
Min Max
-30ns
Min Max
WRITE CYCLE
twc
tew
t AS
tWP
tWR
tDW
t DH
twz
tow
tAW
Write Cycle Time 1 2
Chip Select Valid to
End of Write
Address
Setup Time
Write Pulse width
Write
Recovery Time
Data Valid to
End of Write
Data Hold Time
Write Enable to
Output in High Z (2)
Output Active from
End of Write (2)
Address Valid to
End of Write
10
10
10
15
13
12
13
20
17
16
10
17
25
20
20
15
20
10
30
25
25
20
25
12
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
QUALITY SEMICONDUCTOR INC.
QS83280
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2,3)
L- tRC (5)
■
Tl
AVEFORMS - READ CYCLE NO. 2 (1,3)
t RC (5)
Vcc SUPPLY Ice
CURRENT
Notes:
1 . WE~is high for Read cycle.
2. " CSHs low for Read cycle #1 .
3. Address Is valid to or coincident with Cl> transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
2-87
QS83280
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE controlled timing)
r* ^ *i
ADRS
C5
WE
DATA OUT
DATA IN
4 IAS ^ L
t AW
tWZ(6)
+\
tow
^ tDW tDH ^
|( DATA VALId" ^ )
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,5 C5 controlled timing)
^ *
ADRS
€5
WE
DATA IN
X
t AW
t AS
tew
S
tDW
tWR
< ►
tDH
DATA VALID
Notes:
1 . WE or CS must be high during address transitions.
2. A write occurs during the overlap of a low CS and a low WE
3. t WR is measured from the earlier of and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE tow transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
X
=
QUALITY SEMICONDUCTOR INC.
=
QS83283
e High-Speed CMOS QS83283
32Kx8 SRAM with advance
Fast Address Bit information
FEATURES/BENEFITS
• Equal access and cycle times
• 15ns/20ns/25/30 ns Commercial
• 20ns/25/30 ns Military
• Available in 28-pin 300/600-mil DIP, SOJ
• Military product compliant to MIL-STD-883
DESCRIPTION
The QS83283 is a high-speed 256K SRAM organized as 32K words of 8 bits. It has a fast access
address pin (A10) which allows access to a second word in approximately half the access time for the first
word. This is useful in MIPS R4000 RISC CPU secondary cache applications. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS83283 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
PIN CONFIGURATION
• Fast access on one address bit for MIPS R4000
• 6-Transistor cell for high reliability
• TTL compatible I/O
■ High performance QCMOS™ technology
AO
c
1
28
□
vcc
A1
c
2
27
□
WE
A2
c
3
26
□
A14
A3
c
4
25
□
A13
A4
c
5
24
□
A12
A5
c
6
o
OT
23
□
A11
A6
II
7
22
□
OE
A7
c
8
qT
21
□
A10
A8
c
9
5
Q.
20
□
C5
A9
c
10
19
□
I/08
1/01
c
11
18
□
I/07
I/02
c
12
17
□
I/06
I/03
c
13
16
I/05
GND
II
14
15
□
I/04
ALL PINS TOP VIEW
====^===
QUALITY SEMICONDUCTOR INC.
QS83283
-ITT
■ V
1*1 iJA
2-90
QUALITY
QS83285
Q
Low Power CMOS QS83285
32Kx8 SRAM preliminary
with Common I/O
=
FEATURES/BENEFITS
Ultra low stby. power for battery backup applications • 6-Transistor cell for high reliability
70ns/85ns/1 00ns/1 20ns Commercial
85ns/100ns/120ns Military
Low power, high-speed QCMOS™ technology
Military product compliant to MIL-STD-883
TTL compatible I/O
JEDEC standard pinout
Available in 28-pin 300/600-mil PDIP
DESCRIPTION
The QS83285 is a high-speed 256K SRAM organized as 32K words of 8 bits. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS83285 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
C5
WE
rJE •
I/O ■
3>
262,144 BIT
MEMORY
ARRAY
Write
Read
Read/Write Data I/O
QUALITY SEMICONDUCTOR INC.
QS83285
PIN CONFIGURATIONS
AO
1
w
28
A1
2
27
A2
3
26
A3
4
25
A4
5
24
A5
6
o
23
A6
7
(0
22
A7
8
a."
21
A8
9
5
20
A9
10
19
1/01
11
18
I/02
12
17
I/03
13
16
GNDC
14
15
□ A14
□ A13
□ A12
□ A11
□ 0~E
"3 A10
□ C5
□ I/08
□ I/07
□ I/06
□ I/05
□ I/04
■ 111 'II nUUIli Li illUJ „ iMCTBOTWB
!
ALL PINS TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE
Pin Name
I/O
Function
A
I
Address
1/01 - 1/08
I/O
Data
C5
I
Chip Select
WE
I
Write Enable
0"E
I
Output Enable
Function
C5
WE
01
I/O
Power
Deselect
H
X
X
HighZ
Standby
Read
L
H
L
Data out
Active
Write
L
L
X
Data In
Active
Output
Disable
L
H
H
HighZ
Active
2-92
QUALITY
R INC.
QS83285
ABSOLUTE MAXIMUM RATINGS
'a . ■-•••IS'
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to VCc + 0-5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
TSTG Storage Temperature, COM -65° to +125°C
TBIAS Temperature Under Bias, MIL -65° to +135°C
TSTG Storage Temperature, MIL -65° to +155°C
j J ■* l i lucini J IRI
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Ta=+25°C,f=1 MHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY SEMICONDUCTOR INC.
2-93
QS83285
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vll
Input LOW voltage (1 )
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
Ion = -1 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 2.1 mA, Vcc = MIN
0.4
0.4
| Hi |
Input Leakage
Vcc = MAX,
Vin = GNDtoVcc
2
4
uA
| to |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
Chip deselcted
2
4
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
Max
Max
Unit
Symbol
Parameter
Max
Max
Unit
COM.
MIL.
COM.
MIL.
led
Operating Current,
CS = Vil, WE = Vih,
Other inputs = Vih/Vil
Vcc = MAX
Outputs open
f = max, 70/85ns
55
60
mA
Isb2
Standby Current,
Vcc = 2.0-5.5V
CS > Vcc-0.2V
Vin < 0.2V or
Vin > Vcc -0.2V
1.0
5.0
uA
Icc2
Operating Current.
CS = Vil, WE = Vih,
Other inputs = Vih/Vil
Vcc = MAX
Outputs open
f = max, 100-150 ns
45
50
Isb3
Standby Current,
Vcc = 2.0V
"CS > Vcc-0.2V
Vin < 0.2V or
Vin > Vcc -0.2V
0.5
3.0
Isb1
Standby Current,
Vcc = MAX
Outputs open
CS > Vih
3.0
4.0
2-94
QUALITY SEMICONDUCTOR INC.
QS83285
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
70ns
85ns
100ns
120ns
(D
Min
Max
Min
Max
Min
Max
Min
Max
. ,, , J
READ CYCLE
t RC
Read Cycle Time
70
85
-
100
120
t AA
Address
70
85
100
120
Access Time
tACS
Chip Select
70
85
100
120
AccessTime
tOH
Output Hold
5
5
5
5
from Address
tCLZ
Chip Select to
10
-
10
-
10
-
10
-
Output in Low Z (2)
tCHZ
Chip Select to
30
30
35
40
Output in High Z (2)
tOE
Output Enable
35
45
50
60
Access Time
tOHZ
Output enable to
30
30
35
40
output in High Z
tOLZ
Output enable to
5
5
5
5
output in Low Z
; li.''
tPU
Chip select to
0
0
0
0
Power-Up Time (2)
tPD
Chip select to
Power-Down Time
70
85
100
120
rug » w .- - , \ ' .'•
Notes:
1) See Test Circuit and Waveforms. Minim urns guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC. 2-95
QS83285
Commercial TA = 0° C to 70°C, Vcc = 5.0V+1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(1)
70ns
85ns
100ns
120ns
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
twc
\A/i-i+j-i fNfjiln Timn
WN18 uycie 1 Im8
70
85
100
120
tew
Chip Select Valid to
FnH nf Writ ft
tllU *JI VYlllfc*
65
75
90
100
tAS
Address
?ati m lima
ooiup l mm
0
0
0
0
■
tWP
Write Pulse width
55
65
70
80
tWR
Write
Recovery Time
0
0
0
0
tDW
Data Valid to
End of Write
35
40
45
50
tDH
Data Hold Time
0
0
0
0
twz
Write Enable to
Output in High Z (2)
30
30
35
40
tow
Output Active from
End of Write (2)
5
5
5
5
tAW
Address Valid to
End of Write
65
75
90
100
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
■
2-96 QUALITY SEMICONDUCTOR INC.
=
QS83285
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2,3)
N tRC (5)
C5
ADRS
ADDRESS VALID
t AA
'« t0H »
DATA OUT
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
N L5C(5) ^
■
ADRS
OE
DATA OUT
ADDRESS VALID
t ACS
tOE
^iOLZ^
X
—
tOHZ (4).
t CHZ (4) |
j£ *^|C *^^A VALID*-
tPU
Vcc SUPPLY Ice
CURRENT |sb
tPD
Notes:
1 . WE~is high for Read cycle.
2. " C5"is low for Read cycle #1 .
3. Address is valid to or coincident with C5 transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
QUALITY SEMICONDUCTOR INC.
QS83285
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE
* im
DATA IN
C DATA VALID
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,5 C5 controlled timing)
ADRS
WE
DATA IN
twc
tAW
t AS
"1
tew
:
tDW
tWR
< ►
DATA VALID
Notes- ^ - d8l ™ ;
1 . WE or CS must be high during address transitions.
2. A write occurs during the overlap of a low CS and a low WE.
3. t WR is measured from the earlier of CS and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
2-98
QUALITY
:tor INC.
QS83289
High-Speed CMOS
32Kx8 SRAM with
Fast Chip Select
QS83289
ADVANCE
INFORMATION
FEATURES/BENEFITS
Equal access and cycle times
12ns/15ns/20ns/25/30ns Commercial
15ns/20ns/25/30ns Military
Available in 28-pin 300/600-mil DIP, SOJ
Fast chip select access
6-Transistor cell for high reliability
TTL compatible I/O
High performance QCMOS™ technology
• Military product compliant to MIL-STD-883
DESCRIPTION
The QS83289 is a high-speed 256K SRAM organized as 32K words of 8 bits. It achieves a fast chip
select access time by not powering down the array when the chip is disabled. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS83289 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
PIN CONFIGURATION
AO
C
1
28
□
vcc
A1
c
2
27
□
WE
A2
c
3
26
□
A14
A3
c
4
25
□
A13
A4
c
5
SOJ
24
□
A12
A5
c
6
23
□
A11
A6
c
7
22
□
fJE
A7
c
8
qT
21
□
A10
A8
c
9
Q
Q.
20
□
C5
A9
c
10
19
□
I/08
1/01
□
11
18
□
I/07
I/02
c
12
17
□
I/06
I/03
c
13
16
□
I/05
gndC
14
15
□
I/04
ALL PINS TOP VIEW
QUALITY SEMICONDUCTOR INC.
2-99
QS83289
-
■
2-100 QUALITY SEMICONDUCTOR INC.
QS83290
Q
High Speed CMOS
32Kx9 SRAM
with Common I/O
QS83290
ADVANCE
INFORMATION
3
FEATURES/BENEFITS
• 15/20/25/30ns Commercial
• 20/25/30ns Military
• TTL compatible I/O
• Available in 32-pin 300/600-mil DIP, SOJ
Equal access and cycle times
Military product compliant to MIL-STD-883
6-Transistor cell for high reliability
JEDEC standard pinout
DESCRIPTION
The QS83290 is a high-speed 288K SRAM organized as 32K words of 9 bits. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS83290 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
PIN CONFIGURATIONS
NCC
1
32
□
vcc
NCC
2
31
□
A
AC
3
30
□
CS2
AC
4
29
□
WE
AC
5
28
□
A
AC
6
->
o
27
□
AO
AC
7
to
26
□
A1
AC
8
qT
25
□
A
AC
9
Q
24
□
0~E
AC
10
23
□
A
AC
11
22
□
C5T
1/01 C
12
21
□
I/09
I/02 C
13
20
□
I/08
I/03 C
14
19
□
I/07
I/04 C
15
18
□
I/06
gndC
16
17
□
I/05
ALL PINS TOP VIEW
QUALITY SEMICONDUCTOR INC.
2-101
QS83290
■
■
■
2-102
QUALITY SEMICONDUCTOR INC.
QS83291
===== =====
High Speed CMOS QS8329i
32Kx9 SRAM advance
with Burst Mode information
FEATURES/BENEFITS
• 32Kx9 Burst Mode SRAM • Optimized for 80486 secondary cache
• 20/25/30/40ns Commercial • 20 ns clock cycle time for 50 MHz systems
• 25/30/40ns Military • Military product compliant to MIL-STD-883
• TTL compatible I/O • 6-Transistor cell for high reliability
• Available in 32-pin 300/600-mil DIP, SOJ • JEDEC standard pinout
DESCRIPTION
The QS83291 is a high-speed 288K SRAM with burst mode operation organized as 32K words of 9
bits. It is a clocked device with a 80486 CPU compatible 4-word burst counter and is optimized for
performance in 80486 secondary cache systems. Clock cycle times down to 20 ns allow use in 50 MHz
systems. It is manufactured in a high-performance CMOS process, and it based on a 6-transistor cell
design for high reliability of data retention. Low operating power and excellent latch-up and ESD
protection are provided.
PIN CONFIGURATIONS
ADSC
32
□
vcc
CLKC
2
31
□
A
AC
3
30
□
C5
AC
4
29
□
WE
AC
5
28
□
A
A C
6
->
o
27
□
AO
AC
7
26
□
A1
AC
8
25
□
A
AC
9
of
5
24
□
D~E
AC
10
23
□
A
AC
11
22
□
I/09
i/oi C
12
21
□
GND
I/02 C
13
20
I/08
I/03 C
14
19
□
I/07
I/04 C
15
18
□
I/06
gndC
16
17
1
I/05
ALL PINS TOP VIEW
=================
QUALITY SEMICONDUCTOR INC.
2-103
QS83291
■
■
■
. ■
■
2-104
QUALITY SEMICONDUCTOR INC.
QS86440
Q
High-Speed CMOS
64Kx4 SRAM
with Common I/O
QS86440
ADVANCE
INFORMATION
FEATURES/BENEFITS
• High Speed Access and Cycle times
• 12ns/15ns/20ns/25ns Commercial
• 15ns/20ns/25ns/35ns Military
• TTL compatible I/O
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883, Class B
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
Available in 24-pin DIP, 24-pin ZIP,
24-pin 300 mil SOJ & 28-pin LCC
Low Standby current
JEDEC standard pinout
DESCRIPTION
The QS86440 is a high-speed 256K SRAM organized as 64K words of 4 bits. It is manufactured in a
high-performance CMOS process, and it based on a 6-transistor cell design for high reliability of data
retention. The high-speed access times of the QS86440 make it useful in cache data RAM, cache tag
RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low
operating power and excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
C5
WE
I/O
262,144 BIT
MEMORY
ARRAY
j— v Write
QUALITY SEMICONDUCTOR INC.
2-105
QS86440
PIN CONFIGURATIONS
A1
24
t
2
23
1—
L
3
22
c
4
21
c
5
20
c
6
o
(0
19
c
18
c
8
qT
17
c
9
5
16
c
10
15
c
11
1 4
c
12
13
Vcc
A15
A14
A13
A12
A11
A10
I/O 4
I/O 3
I/O 2
1/01
WE
■
■
ALL PINS TOP VIEW
* For ZIP, LCC pinouts contact factory
FUNCTION TABLE
PIN DESCF
tIPTIO
N
Pin Name
I/O
Function
A
I
Address
1/01 - 1/04
I/O
Data
C5
I
Chip Select
WE
I
Write Enable
C3
WE
I/O
Power
Function
H
X
HighZ
Standby
Deselect
L
H
Data Out
Active
Read
L
L
Data In
Active
Write
2-106
QUALITY SEMICONDUCTOR INC.
QS86440
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to Vcc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
TSTG Storage Temperature, COM -65° to +125°C
TBIAS Temperature Under Bias, MIL -65° to +135°C
TSTG Storage Temperature, MIL -65° to +155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SOJ Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0 V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
Note: Capacitance is measured at characterization but not tested at final production.
QUALITY SEMICONDUCTOR INC.
2-107
QS86440
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
Cum hnl
w y 1 1 1 i
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA, Vcc = MIN
0.4
0.4
IJJ
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
HA
1 Ho]
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-12
1 5
-20
-25/-35
Unit
C
M
C
M
C
M
C
M
led
Static Operating
Current, Vcc = MAX
Outputs open
CS < Vil, f = 0
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
170
165
175
155
165
145
155
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS^Vih, f = f MAX
90
100
90
100
90
100
90
100
Isb1
Full Standby
Current, Vcc = MAX
Outputs open
CS>Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
2-108
QUALITY SEMICONDUCTOR INC.
QS86440
=
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±1 0% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-12
(3)
-15(3)
-20
-25
-35
(D
Min
Mill
May
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
12
1 5
1 9
25
-
35
t AA
Address
Access Time
12
1 5
1 9
25
-
35
tACS
Chip Select
12
1 5
1 9
25
35
Access Time
tOH
Output Hold from
Address Change
2
"
2
3
3
3
tLZ
Chip Select to
2
2
2
2
3
Output in Low Z (2)
tHZ
Chip Select to
5
7
8
10
15
Output in High Z (2)
tPU
Chip Select to
0
0
0
0
0
Power Up Time (2)
tPD
Chip Select to
12
15
19
25
35
Power Down Time (2)
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5%. Commercial Only-Preliminary Data.
2-109
QS86440
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V+10%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-12
(3)
•15(3)
-20
-25
-35
(D
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
twc
Write Cycle Time
12
15
1 9
25
35
tew
Chip Select Valid to
end of writ©
10
13
1 7
20
30
tAW
Address Valid to
end ot Write
1 0
-
13
1 7
20
■
30
tAs]
Address
Setup Time
0
0
0
0
u
tWP
Write Pulse width
10
I _
12
_
16
_
20
_
30
_
tWR
Write
Recovery Time
0
0
0
0
0
tDW
Data Valid to
End of Write
6
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
5
6
7
8
12
tow
Output Active from
End of Write(2)
2
2
2
2
3
rt
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
2-110
QUALITY SEMICONDUCTOR INC.
QS86440
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
tRC (5)
C5
ADRS
X
ADDRESS VALID
t AA
DATA OUT
DATA VALID
xz
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
U* tRC (5) *
ADRS
DATA OUT
s
ADDRESS VALID
tACS
t H/ (4)
VALID
Vcc SUPPLY Ice
CURRENT |gb
a:
■ .
Notes:
1 . WFis high for Read cycle.
2. " C3~is low for Read cycle #1 .
3. Address is valid to or coincident with C5 transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
QUALITY SEMICONDUCTOR INC.
2-111
QS86440
=
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE
twc_
ADRS
DATA IN
TIMING WAVEFOR
ADRS
WE
DATA IN
| ^™ \
LWC.
LS controlled timing)
tAW
—
t AS
tew
tWR
•4 — ►
y
tDW
DATA VALID
Notes:
1 . WE or must be high during address transitions.
2. A write occurs during the overlap of a low CS and a low WE.
3. t WR is measured from the earlier of CS and WE going high to end of the write cycle.
4. During this period the I/O pins are in the output state and input signals must not be applied.
5. If the C5 low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
QUALITY SEMICONDUCTOR INC.
QS86442
Q
High-Speed CMOS
64Kx4
Cache TAG RAM
QS86442
ADVANCE
INFORMATION
FEATURES/BENEFITS
• Fast Match and Access times
• Access time of15ns/20ns/25ns/35ns Commercial
• Match time of 1 5ns/20ns/25ns/35ns Commercial
• Low power, high-speed QCMOS™ technology
6-Transistor cell for high reliability
MATCH signal with positive polarity
Available in 300-mil, 28-pin DIP and SOJ
Military product compliant to MIL-STD-883
DESCRIPTION
The QS86442 is a high-speed 256K TAG RAM organized as 64K words of 4 bits. It is manufactured in a
high-performance CMOS process, and it is based on a 6-transistor cell design for high reliability of data
retention. Low operating power and excellent latch-up and ESD protection are provided.
PIN CONFIGURATIONS
NC
c
1
28
□ Vcc
AO
c
2
27
□ A15
A1
c
3
26
□ A14
A2
4
25
□ A13
A3
c
5
24
□ A12
A4
c
6
23
□ A11
A5
c
7
o
OT
22
□ A10
A6
c
8
q."
5
21
□ NC
A7
c
9
20
□ MATCH
A8
c
10
19
□ I/04
A9
c
11
18
□ I/03
CE
c
12
17
□ I/02
QE
c
13
16
□ 1/01
GND
c
14
15
□ we
ALL PINS TOP VIEW
QUALITY !
JCTOR INC.
2-113
QS86442
======
2-114
QUALITY SEMICONDUCTOR INC.
QS86444, QS86449
Q
High-Speed CMOS
64Kx4 SRAM
with Separate I/O
QS86444
QS86449
ADVANCE
INFORMATION
FEATURES/BENEFITS
High Speed Access and Cycle times
15ns/20ns/25ns Commercial
20ns/25ns/35ns Military
TTL compatible I/O
Low Standby current
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
Available in 28-pin DIPs, 28-pin 300 mil
Low power, high-speed QCMOS™ technology
Military product compliant to MIL-STD-883
DESCRIPTION
The QS86444 and QS86449 are high-speed 256K SRAMs organized as 64Kx4 with separate read and
write data buses. In the 86444, the read data outputs follow the inputs during a write; in the 86449, the
outputs are disabled during a write. The 86444 and 86449 are manufactured in a high-performance
CMOS process, and they are based on a 6-transistor cell design for high reliability of data retention.
Their high-speed access times make them useful in cache data RAM, cache tag RAMs, high-speed
scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low operating power and
excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
Di
WE
C5
7SD-
262,144 BIT
MEMORY
ARRAY
Write
Read
Read/Write Data I/O
-*)>-► Yl
Note:
WE is not connected to Output Enable Gate 2 in the 86444.
WE is connected to Output Enable Gate 2 as shown in the 86449.
s
QUALITY SEMICONDUCTOR INC
2-115
QS86444, QS86449
PIN CONFIGURATIONS
-
ALL PINS TOP VIEW
2-116
QUALITY SEMICONDUCTOR INC
QS86446
Q
High-Speed CMOS
64Kx4 SRAM
with Output Enable
QS86446
ADVANCE
INFORMATION
FEATURES/BENEFITS
• High Speed Access and Cycle times
• 12ns/15ns/20ns/25ns Commercial
• 15ns/20ns/25ns/35ns Military
• TTL compatible I/O
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883, Class B
• 6-Transistor cell tor high reliability
• Ideal for reliable.dense memory systems
• Available in 28-pin DIP & 300 mil SOJ
• JEDEC standard pinout
• Low Standby current
DESCRIPTION
The QS86446 is a high-speed 256K SRAM organized as 64Kx4 with an output enable. It is
manufactured in a high-performance CMOS process, and it based on a 6-transistor cell design for high
reliability of data retention. The high-speed access times of the QS86446 make it useful in cache data
RAM, cache tag RAMs, high-speed scratchpad memories, look-up tables, pipelined DSP and bit-slice
systems. Low operating power and excellent latch-up and ESD protection are provided.
FUNCTIONAL BLOCK DIAGRAM
Address
is
262,144 BIT
MEMORY
ARRAY
C5.
WE
0~E
I/O ■
Write
Read
Read/Write Data I/O
QUALITY SEMICONDUCTOR INC.
2-117
QS86446
=====
PIN CONFIGURATIONS
□ Vcc
□ A15
■
ALL PINS TOP VIEW
* For LCC pinout contact factory
PIN DESCRIPTION
FUNCTION TABLE
Pin Name
I/O
Function
C3
WE
I/O
Power
Function
A
I
Address
H
X
HighZ
Standby
Deselect
1/01 - 1/04
I/O
Data
L
H
Data Out
Active
Read
C5
I
Chip Select
L
L
Data In
Active
Write
WE
I
Write Enable
o~e
I
Output enable
■
2-118
=
QUALITY SEMICONDUCTOR INC.
QS86446
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to Vqc + 0.5V
DC Input Voltage V| -0.5V to VCc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Output Current Max. sink current/pin 50 mA
DC Output Current Max. source current/pin 30 mA
TBIAS Temperature Under Bias, COM -65° to +125°C
-65°to+125°C
-65°to+135°C
-65° to +155°C
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to the maximum ratings for extended periods may
affect reliability.
CAPACITANCE
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V PDIP Pkg.
3
6
PF
Cin
Input Capacitance
Vin = 0 V SO J Pkg.
2.5
5
PF
Cout
Output Capacitance
Vout = 0 V PDIP Pkg.
7
PF
Cout
Output Capacitance
Vout = 0 V SOJ Pkg.
7
PF
QUALITY SEMICONDUCTOR INC.
2-119
QS86446
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH voltage
Logic High for All Inputs
2.2
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -4 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8 mA, Vcc = MIN
0.4
0.4
l||
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
5
10
UA
I "o |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
5
10
Notes:
1 . Transient inputs with Vil not more negative than -3.0 volts are permitted for pulse widths < 20 ns.
POWER SUPPLY CHARACTERISTICS
Commercial TA = 0° C to 70°C, Vcc = 5.0V+10% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Vic = 0.2 V, Vhc = Vcc - 0.2V At f = 0, no input lines switch; At f = f MAX, RAM is cycling at 1 / 1 RC
Symbol
Parameter
-12
1 5
-20
-25/-35
Unit
C
M
C
M
C
M
C
M
Icc1
Static Operating
Current, Vcc = MAX
Outputs open
CS < Vil, f = 0
100
120
100
120
100
120
100
120
mA
ICC2
Dynamic Operating
Current, Vcc = MAX
Outputs open
CS<Vil, f = fMAX
170
165
175
155
165
145
155
Isb
TTL Standby
Current, Vcc = MAX
Outputs open
CS>Vih, f = f MAX
90
100
90
100
90
100
90
100
Isbl
Full Standby
Current, Vcc = MAX
Outputs open
CS>Vhc, f = 0
Vin < Vic or Vin > Vhc
15
20
15
20
15
20
15
20
2-120
QUALITY SEMICONDUCTOR INC.
QS86446
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
See Read Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
-12
(3)
-15(3)
-20
-25
-35
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
READ CYCLE
t RC
Head uycie l ime
1 2
15
1 9
25
3b
t AA
Address
12
15
19
25
35
Access Time
t ACS
Chip Select
1 2
15
19
25
35
Access Time
tOH
Output Hold from
2
2
3
3
3
Address Change
tCLZ
Chip Select to
2
-
2
-
2
-
2
-
3
-
Output in Low Z (2)
tCHZ
Chip Select to
5
7
8
10
15
Output in High Z (2)
tPU
Chip Select to
0
0
0
0
0
Power Up Time (2)
tPD
Chip Select to
Power Down Time (2)
12
15
19
25
35
tOE
Output Enable to
6
6
8
10
14
Data Valid
tOLZ
Output Enable to
2
2
2
2
2
Output in Low-Z (2)
tOHZ
Output Enable to
Output in High-Z (2)
4
5
7
8
10
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5%. Commercial Only-Preliminary Data.
QUALITY SEMICONDUCTOR INC.
2-1
QS86446
-
Commercial TA = 0° C to 70°C, Vcc = 5.0V±10% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
See Write Timing Diagrams. All values in nanoseconds unless otherwise noted
Symbol
Parameter
(1)
-12 (3)
-15(3)
-20
-25
-35
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
WRITE CYCLE
twc
Write Cycle Time
12
15
19
25
35
tew
Chip Select Valid to
End of Write
1 0
13
1 7
20
30
t AW
Address Valid to
End of Write
1 n
1 "\
•j 7
20
30
t AS
Address
Setup Time
o
o
0
0
o
t WP
Write Pulse width
1 0
1 2
1 6
20
30
tWR
Write
Recovery Time
0
0
0
0
0
tDW
Data Valid to
End of Write
6
8
10
13
18
t DH
Data Hold Time
0
0
0
0
0
twz
Write Enable to
Output in High Z (2)
5
6
7
8
12
tow
Output Active from
End of Write(2)
2
2
2
2
3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) For Vcc±5% Commercial Only-Preliminary Data
2-122
QUALITY SEMICONDUCTOR INC.
TIMING WAVEFORMS - READ CYCLE NO. 1 (1,2)
tRC (5)
C5
ADRS
DATA OUT
X
ADDRESS VALID
« 10H »
DATA VALID
TIMING WAVEFORMS - READ CYCLE NO. 2 (1,3)
_tRC(
ADRS "
Vcc SUPPLY Ice
CURRENT
Notes:
■
1 . WE"is high for Read cycle.
2. " CSls low for Read cycle #1 .
3. Address is valid to or coincident with CS transition time for Read Cycle #2.
4. Transition to Hi-Z is measured ± 200 mV change from the prior steady state voltage.
5. All read timings are referenced from the last valid address to the first transitioning address.
QUALITY SEMICONDUCTOR INC.
2-123
QS86446
TIMING WAVEFORMS-WRITE CYCLE No. 1 (1,2,3 WE
^ t wc
DATA IN
TIMING WAVEFORMS-WRITE CYCLE No. 2 (1,2,3,5 C5 controlled timing)
ADRS
C5
WE
DATA IN
twc
-
3c
tAW
tew
tDW
twi
DATA VALID }
Notes: ~i ,
1 . WE or must be high during address transitions.
2. A write occurs during the overlap of a low and a low WE.
3. t WR is measured from the earlier of and WE going high to end of the write cycle.
4. During this period the IAD pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the output remains
in the high impedance state.
6. Transition to Hi-Z is measured ± 200 mV change from the previous steady state voltage.
■
—
QUALITY SEMICONDUCTOR INC.
2-124
QS86447
Q
High-Speed CMOS
64Kx4 SRAM
with Address Latch
QS86447
ADVANCE
INFORMATION
FEATURES/BENEFITS
• High Speed Access and Cycle times
• 15ns/20ns/25ns/35ns Commercial
• Common I/O with Output Enable
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883
• 6-Transistor cell for high reliability
• Ideal for reliable.dense memory systems
• Available in 300-mil, 28-pin DIP and SOJ
• Address input latches with single clock control
• TTL compatible I/O
DESCRIPTION
The QS86447 is a high-speed 256K SRAM organized as 64K words of 4 bits. It is manufactured in a
high-performance CMOS process, and it is based on a 6-transistor cell design for high reliability of data
retention. The QS86447 input address latches make it useful in cache data RAM, cache tag RAMs, and
other high speed memory applications. Low operating power and excellent latch-up and ESD protection
are provided.
PIN CONFIGURATIONS
LE
□
1
28
□ Vcc
AO
c
2
27
□ A15
A1
c
3
26
□ A14
A2
c
4
25
□ A13
A3
c
5
24
□ A12
A4
c
6
23
□ A11
A5
c
7
o
CO
22
□ A10
A6
□
8
21
□ NC
A7
c
9
a
5
20
□ NC
A8
c
10
19
□ I/04
A9
c
11
18
□ I/03
CE
c
12
17
□ I/02
0~E
c
13
16
□ 1/01
GND
c
14
15
□ WE
ALL PINS TOP VIEW
QS86447
■
■
■
■
2-126
QS86448
=
Q
High-Speed CMOS
64Kx4 SRAM
with Address Register
QS86448
ADVANCE
INFORMATION
FEATURES/BENEFITS
• Fully synchronous, single clock operation
• 15ns/20ns/25ns/35ns Commercial
• Self timed write with late write abort
• Low power, high-speed QCMOS™ technology
• Military product compliant to MIL-STD-883
6-Transistor cell for high reliability
Ideal for reliable.dense memory systems
Available in 300-mil, 28-pin DIP and SOJ
Registered Address inputs
TTL compatible I/O
======
DESCRIPTION
The QS86448 is a high-speed 256K SRAM organized as 64K words of 4 bits. It is manufactured in a
high-performance CMOS process, and it is based on a 6-transistor cell design for high reliability of data
retention. The QS86448 input address register makes it useful in cache data RAM, cache tag RAMs,
and other high speed memory applications. Low operating power and excellent latch-up and ESD
protection are provided.
PIN CONFIGURATIONS
CLK
c
1
28
□ Vcc
AO
c
2
27
□ A15
A1
c
3
26
□ A14
A2
c
4
25
□ A13
A3
c
5
24
□ A12
A4
c
6
—>
23
□ A11
A5
c
7
o
22
□ A10
A6
c
8
21
□ NC
A7
c
9
a."
20
□ NC
A8
c
10
Q
19
□ I/04
A9
E
11
18
□ I/03
5W
c
12
17
□ I/02
OE
c
13
16
□ 1/01
GND
c
14
15
□ AW
ALL PINS TOP VIEW
QUALITY SEMICONDUCTOR INC.
2-127
QS86448
■
2-128
QUALITY SEMICONDUCTOR
QS812880
Q
High-Speed CMOS
128Kx8 SRAM
QS812880
ADVANCE
INFORMATION
FEATURES/BENEFITS
Equal access and cycle times
20ns/25ns/30 ns Commercial
25ns/30 ns Military
Common I/O with output enable
Military product compliant to MIL-STD-883
High performance QCMOS™ technology
Dual chip select
6-Transistor cell for high i
TTL compatible I/O
High performance QCMOS™ technology
Available in 400-mil 32-pin PDIP, 32-pin SOP,
& 32-pin SOJ with JEDEC standard pinout
DESCRIPTION
The QS812880 is a high-speed 1024K SRAM organized as 128K words of 8 bits. It has two chip select
control lines, and common I/O with output enable. It is manufactured in a high-performance CMOS
process, and it based on a 6-transistor cell design for high reliability of data retention. The high-speed
access times of the QS81280 make it useful in cache data RAM, cache tag RAMs, high-speed
scratchpad memories, look-up tables, pipelined DSP and bit-slice systems. Low operating power and
excellent latch-up and ESD protection are provided.
PIN CONFIGURATIONS
ALL PINS TOP VIEW
QUALITY SEMICONDUCTOR INC.
2-129
QS812880
■
■
■
2-130
:
QUALITY SEMICONDUCTOR INC.
This page was left Intentionally blank
QUALITY :
=
QUALITY SEMICONDUCTOR INC.
General Information 1
Static RAM Products 2
FCT-T Logic Products 4
QuickSwitch Products 5
Application Notes 6
Quality And Reliability 7
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
=
QUALITY SEMICONDUCTOR INC.
FIFO Table of Contents
FIFO MEMORY DATA SHEETS
Page
FIFO Ordering Information 3-3
Fl FO Test Config uration 3-4
QS7201 12 51 2x9 and 1 Kx9 FIFO 3-5
QS7203/4 2K and 4Kx9 FIFO 3-21
QS721 1 12 51 2x9 and 1 Kx9 FIFO with Output Enable 3-39
QS7223/4 2Kx9 and 4Kx9 Clocked FIFO 3-53
QS7306 64Kx4 Ultra Deep FIFO 3-67
QS731 6 64Kx4 Burst Mode Dual Port RAM 3-69
QUALITY SEMICONDUCTOR INC. 3-1
FIFO Table of Contents
-
3-2 QUALITY SEMICONDUCTOR INC.
FIFO Ordering Information
QS8XXX XXX XX X
1
Temperature
Range
A Package type
_| Speed
(Access time)
Device Type
;
Processing;
Blank - Standard
B - MIL-STD 883
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
QUALITY SEMOCONDUCTOR INC.
3-3
FIFO Test Configuration
+5V
1.1K £2
To Output Pin q
680 £1
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
30 pF* * Includes jig and scope
capacitances
3-4
QUALITY
QS7201, QS7202
Q
High Speed CMOS
9-bit FIFO
Buffer Memories
512x9:
1Kx9:
QS7201
QS7202
FEATURES/BENEFITS
• 15 ns flag and data access times
• Fully Asynchronous Read and Write
• Zero fall-through time
• Expandable in depth with no speed loss
• TTL input and output level compatible
• 40 MHz cycle time
• Retransmit capability
• Dual Port RAM-based cell using 6T technology
■ Available in 300 mil/600 mil PDIP, SOIC, SOJ,
300 mil/600 mil CERDIPs, PLCC, LCC
Military product compliant to MIL-STD-883, Class B • Low Power with Industry standard pinouts
DESCRIPTION
The QS7201 and QS7202 are 512x9 and 1Kx9 FIFOs respectively. These FIFOs use a dual-port RAM
based architecture and having independent read and write pointers. This allows high speed and zero
fall-through time. The read and write pointers are incremented on the rising edges of the Read and Write
lines. The flag circuitry is based on a reliable sequential design giving precise half-full, full, and empty
conditions. These flags also prevent the FIFO from being written into when full or being read from when
empty. These FIFOs are easily cascadable to any depth and expandable to any width. There is no speed
penalty for expansion. Retransmit capability is provided. Retransmits resets the read pointer to zero, and
is useful for data communications and digital filtering applications.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
READ
CONTROL
R"5
FC/RT
XI
RESET
LOGIC
EXPANSION
LOGIC
WRITE
POINTER
READ
POINTER
FLAG
LOGIC
EF
FF
HF
DATA IN
D0-D8
DATA OUT
Q0-Q8
DUAL PORT
RAM ARRAY
512X9
1024X9
V
f
Note: XC3 and HF share the same pin so the half-full flag is available only in standalone, not dep Ih expansion mode .
QUALITY SEMICONDUCTOR INC.
=
QS7201, QS7202
O O •* W
£ Z > Q Q
PIN DESCRIPTIONS
Name
I/O
Description
Di
I
Data Inputs
Qi
0
Data Outputs
H
I
Read Clock
W
I
Write Clock
EF
0
Empty Flag
FF
0
Full Flag
Name
I/O
Description
I
Reset
FDRT
I
First Load/Retransmit
I
Expansion Clock In
XC7RF
0
Expansion Clock Out/
Half Full Flag
3-6 QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
FUNCTION TABLES
RESET AND RETRANSMIT FUNCTION TABLE
Stand Alone Device or Width Expansion
MODE
INPUTS
INTERNAL STATUS
OUTPUTS
R5
FD
RT
XT
Read Pointer
Write Pointer
EF
FF
HF
Reset
L
X
L
Location Zero
Location Zero
L
H
H
Retransmit
H
L
L
Location Zero
Unchanged
(3)
(3)
(3)
Read/Write
H
H
L
Increment (1)
Increment (2)
(4)
(4)
(4)
Notes:
(1) The Read Pointer will increment if the FIFO is not empty.
(2) The Write flag will increment if the FIFO is not full.
(3) The flags will change after the retransmit operation and will correspond to the read pointer
being at location zero.
(4) The flags will reflect the relative locations of the read and write pointers.
RESET AND FIRST LOAD FUNCTION TABLE
MODE
INPUTS
INTERNAL
STATUS
OUTPUTS
H5~
FC/
RT
XI
Read Pointer
Write Pointer
EF
FF
HF
Reset 1st Device
L
L
(1)
Location Zero
Location Zero
L
H
H
Reset Other Devices
H
H
(1)
Location Zero
Location Zero
(3)
(3)
(3)
Read/Write
H
(2)
(1)
Increment (1)
Increment (2)
(4)
(4)
(4)
Notes
(1) The Expansion In (XT) is connected to the Expansion Out (XD") of the previous device.
(2) The device with FL tied low will receive the first N writes and first N reads, where N is the FIFO size. On the Nth
write, the XO" pulse is sent to the next device to indicate that it will receive the (N+1)th write. Similarly on the Nth
read another XTJpulse is sent to the next device to indicate that it will output the (N+1 ) th read.
(3) The read and write pointers will be activated according to whether the FIFO received a n XO pulse, or whether
they were the first device in the daisy chain. The flags will reflect the empty or full conditions for the individual
FIFOs. To create the composite Full and Empty flags, an OR-ing of the individual flags is required.
(4) The flags will reflect the relative locations of the read and write pointers.
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to Vcc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for pulse width<20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Input Diode Current with V | >Vqc 20 mA
DC Output Diode Current with V0 <0 -50 mA
DC Output Diode Current with Vq >V cc 50 mA
DC Output Current Max. sink current/pin 70 mA
DC Output Current Max. source current/pin 30 mA
Total DC Ground Current (NxlOL +MxAI CC) mA
Total DC VCC Power Supply Current (NxlOH + MxAl CC) mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTG Storage Temperature -65° to +165°C
■
CAPACITANCE
Ta = 25°C, f = 1 MHz
-
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V
5
8
PF
Cout
Output Capacitance
Vout = 0 V
5
8
PF
Note: Capacitance is guaranteed but not tested
3-8
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V+10% Military TA=-55°C to 125°C, VCC=5.0V±10%
Unit
Svmbol
Parameter
Test Conditions
commercial
Military
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.0
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -2 mA, Vcc = MIN
2.4
2.4
lol = 8mA, Vcc=MIN
0.4
0.4
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
1
10
uA
| III |
| to |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
10
10
Notes:
1 . Transient inputs with Vil not more negative than -1 .5 volts are permitted for pulse widths < 1 0 ns
POWER SUPPLY CHARACTERISTICS
Commercial TA=0°C to 70°C, VCC=5.0V+1 0% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Vic = 0.2 Volts, Vhc - Vcc - 0.2 Volts
Symbol
Parameter
<3S
>50
Unit
C
M
C
M
led
Operating OperatingCurrent
Vcc = MAX, Outputs open
100
120
100
120
mA
Icc2
Standby Current
15
20
8
15
R = W=RS = FL/RT=Vih
Isb
Power Down Current
5
9
5
9
All Inputs at Vhc or Vic
R = W=RS=FlVRT = Vhc
I
1 q
QUALITY SEMICONDUCTOR INC.
a
QS7201, QS7202
=
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V±10%, TA=0°C to +70°C, MILITARY VCC=5V±10%, TA=-55°C to +125°C
Symbol
Parameter (1)
Note
-15
-20
-25
-35
-50
-80
-120
Unit
Type
READ CYCLE
f RF
Read Frequency, MHz
2
40
33
28
22
15
10
7
MHz
Min
tRC
Read Cycle Time
25
30
35
45
65
100
140
ns
tA
Read Access Time
15
20
25
35
50
80
120
Max
tRR
Read Recovery Time
10
10
10
10
15
20
20
Min
tRPW
Read Pulse Width
1
15
20
25
35
50
80
120
t RLZ
TTData Bus Low Z
2
3
3
3
3
3
3
3
tWLZ
W Data Bus LowZ
2,3
3
3
3
3
3
3
3
tDV
TThigh to Data Hold Time
5
5
5
5
5
5
5
t RHZ
TTto Data High Z
14
18
18
20
30
35
35
Max
WRITE CYCLE
fWF
Write Frequency.MHz
2
40
33
28
22
15
10
7
MHz
Min
twc
Write Cycle Time
25
30
35
45
65
100
140
ns
tWPW
Write Pulse Width
1
15
20
25
35
50
80
120
Write Recovery Time
tWR
10
10
10
10
15
20
20
tDS
Write Data Setup Time
9
12
15
18
30
40
40
tDH
Write Data Hold Time
0
0
0
0
0
0
0
RESET AND RETRANSMIT CYCLES
tRSC
Reset Cycle Time
25
30
35
45
65
100
140
ns
Min
tRS
Reset Pulse Width
1
15
20
25
35
50
80
120
tRSS
Reset Setup Time
15
20
25
35
50
80
120
t RSR
Reset Recovery Time
10
10
10
10
15
20
20
t RTC
Retransmit Cycle Time
25
30
35
45
65
100
140
t RT
Retransmit Pulse Width
1
15
20
25
35
50
80
120
t RTS
Retransmit Setup Time
2
15
20
25
35
50
80
120
t RTR
Retransmit Recovery
10
10
10
10
15
20
20
Notes: These timings are measured as defined in AC Test Conditions
1 . Pulse widths less than the specified minimum value may upset the internal pointers and are not allowed.
2. These values are guaranteed by design and not tested
3. This applies to the read data flow-through mode only.
3-10
QUALITY SEMICONDUCTOR INC.
—
QS7201, QS7202
-
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V+10%, TA=0°C to +70°C, MILITARY VCC=5V+10%, -
=-55°Cto+125°C
Symbol
Parameter (1)
Note
-15
-20
-25
-35
-50
-80
-120
Unit
Type
FLAG TIMING
tREF
Read Low to EF Low
15
20
25
30
45
60
60
ns
Max
t RFF
Read High to FF High
15
20
25
30
45
60
60
t RHF
Read High to HF High
15
20
25
35
45
60
60
t RPE
Read Pulse after EF High
15
20
25
35
50
80
120
tWEF
Write High to EF High
15
20
25
30
45
60
60
tWFF
Write Low to FF Low
15
20
25
30
45
60
60
tWHF
Write Low to HF Low
15
20
25
35
45
60
60
tWPF
Write Pulse after EF Hi
15
20
25
35
50
80
120
t EFL
Reset to EF Low
15
20
25
35
45
60
60
t FFH
Reset to FF High
15
20
25
35
45
60
60
tHFH
Reset to HF High
15
20
25
35
45
60
60
EXPANSION TIMING
tXOL
Read/Write to XO Low
15
20
25
35
50
80
120
ns
Max
tXOH
Read/Write to XO High
15
20
25
35
50
80
120
txi
XlPulse Width
15
20
25
35
50
80
120
tXIR
XI Recovery Time
10
10
10
10
10
10
10
Min
txis
XI Setup Time
10
15
15
15
15
15
15
AC TEST CONDITIONS
+5V
1.1K£2
To Output Pin q
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
680 a ^ ' y
■ Includes jig and scope
capacitances
QUALITY
INC.
3-11
=
QS7201, QS7202
TIMING DIAGRAMS
tRC
1 RPW ■
y
tA ►
t RLZ
Q0-Q8 —
t RR
t RHZ
tDV
Valid Data
W
D0-D8
twc
-tWPW-
y
K t;;:m - !'r:';:
tDS
< ►
tWR
t DH
< *l
||C VaM Data j&
Asynchronous Read and Write Operations
Notes: Read and Write have to be at a HIGH level around the rising edge of Reset. The flags may change during
reset but are valid at t RSC.
Reset Timing
3-12
QUALITY SEMICONDUCTOR INC.
=
QS7201, QS7202
=
R
w
"S X
-*JtWFF
Full Flag Behavior from Last Write to First Read
tRFF^p-
FF
W
— *J t RFF
>
-*-tWPF = tWPW-*
Full Flag and Required Write Pulse at I
Empty
■
;
w
jrr
->UWEF
EF
■ t RPE= T RPW
se Width at Empty Condition
=
QUALITY SEMICONDUCTOR INC.
3-13
QS7201, QS7202
Half Full
tWHF
More Than
Half Full
Half Full
Jr
Half Full Flag Timing
More Than
Half Full
Valid
Flags j
XOT(XT5)
Retransmit Function
Write or Read to Last Physical
Location of Device 1
tXOL
Write or Read to First Physical
Location of Device 2
Note: the Expansion Out of Device 1 is connected to the Expansion In of device 2.
Expansion Out Timing
XT
■
W.-R-
Write to or Read From
First Physical Location of Device
tXIRj^
Expansion In Timing
3-14
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
Data In
D0-D8
W
EF
H
Data Out
Q0-Q8
I ^"oata Valid X~
tWEF
t REF
tRPE
1WLZ
b^t> —
Read Data Flow-Through Mode
Write Data Flow-Through Mode
■
■
■
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
OPERATIONAL DESCRIPTION AND APPLICATION INFORMATION
The QS7201 and QS7202 are 512x9 and 1Kx9 FIFOs respectively. These FIFOs use a dual-port RAM
based architecture and having independent read and write pointers. This allows high speed and zero fall-
through time. The Write line causes data to be written into the FIFO. The Read line causes data to be read
from the FIFO. The Read line also activates the three-state outputs to present the read data. The read and
write pointers are incremented on the rising edges of the Read and Write lines. The flag circuitry is based
on a reliable sequential design giving precise half full, full, and empty conditions. These flags also prevent
the FIFO from being written into when full or being read from when empty. Depth expansion pins are
provided which allow these FIFOs to be expanded in depth without speed penalty. Retransmit capability is
provided. Activating the Retransmit pin resets the read pointer to zero, and is useful for data
communications and digital filtering applications.
SIGNAL DESCRIPTION
PATA INPUTS
D0-D8
The Data In lines Dq to D8 provide data to be written into the FIFO. Note: unused inputs must be tied to
Vcc or Gnd.
CONTROL INPUTS
Reset (R~S)
The Reset input resets the Read and Write pointers and the flags to zero. The FIFO must be reset at
power-up to insure proper operation of the pointers and flags. This is done by asserting the Reset line to a
LOW state, which causes the FIFO flags to be set to empty. This causes the Empty flag is asserted and the
Full and Half Full flags to be deasserted. Read and Write lines must be HIGH for t RSS before and
t RSR after the rising edge of the Reset signal for a valid reset operation.
Write (W)
The Write line caused data to be written into the FIFO. A write cycle is initiated by the falling edge of the
Write signal. A write will occur if the full flag was not asserted, indicative of at least one empty location in the
FIFO. Data is stored in the FIFO on the rising edge of the Write signal using the data set-up and hold times
specified. Data is stored in a sequential manner in the FIFO, and the read and write operations can be
asynchronous. The falling edge of the Write signal asserts the Half full and Full flags when the next word
after half full is written and when the last word has been written, respectively. The rising edge of the Write
line deasserts the empty flag when the first write is performed after an empty or reset condition. When the
Full flag is asserted, subsequent writes are blocked. The user can apply a write pulse after the full
condition is deasserted.
Read (R~)
The Read signal causes data to be read from the FIFO. A read cycle is initiated by the falling edge of the
Read signal. A read is performed if the empty flag is not asserted, indicative of at least one word being
present in the FIFO. The data is accessed in a First-In-First-Out basis asynchronous to the Write
operations. After the Read control is deasserted the data outputs go from a valid state into high-
impedance. The outputs remain in high-impedance until the next read cycle. When all the data is read on
the last read cycle, the Empty flag is asserted, and will inhibit any subsequent reads. The outputs will be in
high-impedance for subsequent read operation until a write occurs that deasserts the Empty flag, allowing
a read cycle to begin. The outputs may also be in high impedance when the FIFOs are cascaded in depth.
In this case, only the active FIFO asserts data , and the other FIFOs data outputs are in high-impedance.
The falling edge of the read signal will set the Empty Flag during the read of the last word in the FIFO. The
rising edge of the Read signal will deassert the Half Full and the Full flags when the FIFO has reached half
full and when the FIFO was full, respectively.
3-16
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
First Load/ Retransmit (FL7RT)
This is a dual purpose input. In the depth expansion mode, this pin indicates the first FIFO device that will
be loaded or read from after a reset operation. In the standalone or width expansion mode (when the the
expansion input is grounded) this pin initiates the a retransmit function.
Retransmit resets the read pointer to zero. The Read and Write signals must be HIGH before and after the
rising edge of the retransmit pulse. The retransmit feature is useful when the same data needs to be read
again without rewriting it into the FIFO. Pulsing retransmit pin will cause the read pointer to be reset to zero
and the previously read data can be read again. The flags will change according to the relative location of
the pointers after the retransmit pulse.
Expansion In (XT)
This is a dual purpose pin. When it is grounded then it indicates that the FIFO is a standalone device.
When it is not grounded, it indicates that the FIFO is in the depth expansion mode. In the depth
expansion mode this pin is connected to the XO pin of the previous device.
DATA OUTPUTS
Data Outputs Qn-Qs
The 9-bit data output bus, Qn-Qs receives the read data from the FIFO. It is active whenever the Read
signal is low. It is in a high impedance state when the Read signal is high. It is also in high impedance when
the FIFO Empty flag is active (i.e., when the FIFO is empty).
CONTROL OUTPUTS
Full Flag (FF)
The Full Flag indicates that the FIFO is full. The Full Flag is asserted when there is only one empty location
in the FIFO and a falling edge of the Write signal initiates the last write operation. The rising edge of the
Read signal deasserts the flag, as at least one location has become available.
Empty Flag (EF)
The Empty Flag indicates the FIFO is empty. It is asserted when there is only one word in the FIFO, and a
falling edge of the Read signal initiates the last read operation. The rising edge of the write signal
deasserts the flag, as one word is now present in the FIFO.
Expansion Out/Half Full flag (X07HF)
This is a dual purpose flag. In the single device mode, the Expansion In is grounded and the Half Full flag
output is present on this pin. Whenever the FIFO is more than half full the flag remains asserted . When
the FIFO is exactly half full and the next falling edge of the Write signal asserts the flag. The rising edge of
read that causes the FIFO to be half full, will deassert the half full flag. It will remain asserted until the FIFO is
half full or less than half full. The name given to the flag is half full, but it is asserted on the one plus the half
full condition.
In the depth expansion mode, the Expansion Out is connected to the Expansion In of the next device.
This causes the next device to perform write or read operations.
QUALITY SEMICONDUCTOR INC.
3-17
OPERATING MODES
SINGLE DEVICE MODE
A FIFO is in standalone mode when the Expansion In control is grounded. In this mode the half full flag is
available on the shared X07HF line. Figure 1 shows the standalone mode and this applies to FIFO width
expansion, as shown in figure 2.
DEPTH EXPANSION MODE
A FIFO is in the depth expansion mode when the Expansion In control is not grounded but tied to the
Expansion Out pin of the previous FIFO. Using the depth expansion mode, the 7201/02 can be easily
cascaded to create FIFOs of larger depth. The devices are cascaded as shown in figure 3. In the depth
expansion mode, the device that receives the first word of data has its First Load input grounded. The
other devices have their First Load inputs in the high state. Two 4-input OR gates are required to create
the composite Full and Empty flags for the FIFO array. In using the depth expansion mode, care must be
taken to keep the traces short between the Expansion In of one device to the Expansion Out of the next
device to minimize crosstalk noise.
FLOW-THROUGH MODES
Flow-through modes refer to the internal operation of the FIFO in empty and full conditions. Flow through
modes allow data to flow directly through the FIFO from input to output under the appropriate empty and
full conditions.
Two types of flow-through modes, a read flow-through and a write flow-through, are supported by the
FIFO. In the read flow-through mode the FIFO is empty, and the read side is waiting for data from a write.
Read flow-through is represented by an empty FIFO that has its Read line held low, and a write occurs.
This rising edge of the Write would deassert the Empty flag and cause valid data to appear on the outputs
after a certain time delay of t wEF + 1 A- Tne Read line Dein9 low would cause the data to be read and also
assert the empty flag once again. The user must raise the Read line in order to increment the read pointer.
In the write flow-through mode, the FIFO is full and the write side is waiting for a word location to be made
available by a read. A write flow-through operation permits the writing of a single word of data immediately
after reading one word of of data from a full FIFO. This is similar to the read flow-through case, and the
Write line must toggled to increment the write pointer.
3-18
QUALITY SEMICONDUCTOR INC.
Data In 0-8
Write Clock
Reset
Full Flag
Data In 0-8
Write Clock
Reset
Data in 9-17
Full
D0-D8 Q0-Q8
W 720X R
R5 FIF0 RT
FF
XT
EF
HF
)► Data Out 0-8
— Read Clock
— Retransmit
->- Empty Flag
Half Full Flag
Fi ure 1. The FIFO in Standalone Mode
D0-D8 Q0-Q8
W 720X R
R5 FIF0 RT
XT
D0-D8 Q0-Q8
W 720X R
R3 FIF0 RT
E"F
HF
FF
^
Data Out 0-8
Read Clock
Retransmit
Data Out 9-17
->• Empty Flag
Half Full Flag
Figure 2. A 18-bit Wide FIFO Using 2 FIFOs
QUALITY SEMICONDUCTOR INC.
QS7201, QS7202
w
Data In
^9
R5
CFF
Xi
Vcc
w
R
7201/2
FF
RS EF
Xo
Vcc
W
FF
R5
Ft
R
7201/2
Xo"
EF
Vcc
Xi
W
Ft
R
7201/2
FF
R5 EF
Xo
Vcc
Xi
w
FC
R
7201/2
FF
^ Xo ^
Data Out
'9
-
■
CEF
Note: The composite Empty and Full flags require the OR-ing of the individual Empty and Full flags, respectively
Figure 3. Building a 4N-deep FIFO Using Four N-deep FIFOs
QS7203, QS7204
=
Q
FEATURES/BENEFITS
High Speed CMOS
9-bit FIFO
Buffer Memories
==
=
2Kx9: QS7203
4Kx9: QS7204
PRELIMINARY
=
15 ns flag and data access times
Fully Asynchronous Read and Write
Zero fall-through time
Expandable in depth with no speed loss
TTL input and output level compatible
Military product compliant to MIL-STD-883, Class B
• 40 MHz cycle time
• Retransmit capability
• Dual Port RAM-based cell using 6T technology
• Available in 300 mil/600 mil PDIP, SOIC, SOJ,
300 mil/600 mil CERDIPs, PLCC, LCC
• Low Power with Industry standard pinouts
DESCRIPTION
The QS7203 and QS72024 are 2Kx9 and 4Kx9 FIFOs respectively. These FIFOs use a dual-port RAM
based architecture and having independent read and write pointers. This allows high speed and zero
fall-through time. The read and write pointers are incremented on the rising edges of the Read and
Write lines. The flag circuitry is based on a reliable sequential design giving precise half-full, full, and
empty conditions. These flags also prevent the FIFO from being written into when full or being read
from when empty. These FIFOs are easily cascadable to any depth and expandable to any width. There
is no speed penalty for expansion. Retransmit capability is provided. Retransmits resets the read
pointer to zero, and is useful for data communications and digital filtering applications.
^— — — — — — — ^— —a — ~— •
FUNCTIONAL
DIAGRAM
Data In
D0-D8
WRITE
CONTROL
READ
CONTROL
R~5
FL7RT
XI
RESET
LOGIC
EXPANSION
LOGIC
WRITE
POINTER
READ
POINTER
DUAL PORT
RAM ARRAY
2K.4KX9
FLAG
LOGIC
ET
FF
RF
Data Out
Q0-Q8
Note: XTJ and RF share the same pin so the half-full flag is available only in standalone, not depth expansion mode .
QUALITY SEMICONDUCTOR INC.
3-21
QS7203, QS7204
PINOUTS
o
co oo O O •* ">
Q Q £ Z > Q Q
ALL PINS TOP VIEW
co co Q 0 ice ^ in
O O g z O O
PIN DESCRIPTIONS
A
Name
I/O
1 1
Description
Name
I/O
Description
Di
1
Data Inputs
1
Reset
Qi
0
Data Outputs
FDRT
1
First Load/Retransmit
R~
1
Read Clock
$
1
Expansion Clock In
W
1
Write Clock
XO/HF
0
Expansion Clock Out/
Half Full Flag
EF
O
Empty Flag
FF
o
Full Flag
3-22
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
FUNCTION TABLES
RESET AND RETRANSMIT FUNCTION TABLE
Stand Alone Device or Width Expansion
MODE
INPUTS
INTERNAL STATUS
OUTPUTS
R"5
FD
RT
XT
Read Pointer
Write Pointer
EF
FF
HF
Reset
L
X
L
Location Zero
Location Zero
L
H
H
Retransmit
H
L
L
Location Zero
Unchanged
(3)
(3)
(3)
Read/Write
H
H
L
Increment (1)
Increment (2)
(4)
(4)
(4)
Notes:
(1 ) The Read Pointer will increment if the FIFO is not empty.
(2) The Write flag will increment if the FIFO is not full.
(3) The flags will change after the retransmit operation and will correspond to the read pointer
being at location zero.
(4) The flags will reflect the relative locations of the read and write pointers.
RESET AND FIRST LOAD FUNCTION TABLE
MODE
INPUTS
INTERNAL STATUS
OUTPUTS
H5
FD
RT
XT
Read Pointer
Write Pointer
EF
FF
HF
Reset 1st Device
L
L
(1)
Location Zero
Location Zero
L
H
H
Reset Other Devices
H
H
(1)
Location Zero
Location Zero
(3)
(3)
(3)
Read/Write
H
(2)
(1)
Increment (1)
Increment (2)
(4)
(4)
(4)
The Expansion In (XT) is
Notes
(D
connected to the Expansion Out (XO) of the previous device.
(2) The device with FC tied low will receive the first N writes and first N reads, where N is the FIFO size. On the Nth
write, the XO pulse is sent to the next device to indicate that it will receive the (N+1 )th write. Similarly on the Nth
read another XOpulse is sent to the next device to indicate that it will output the (N+1 ) th read.
(3) The read and write pointers will be activated according to whether the FIFO received a n XCpulse, or whether
they were the first device in the daisy chain. The flags will reflect the empty or full conditions for the individual
FIFOs. To create the composite Full and Empty flags, an OR-ing of the individual flags is required.
(4) The flags will reflect the relative locations of the read and write pointers.
QUALITY SEMICONDUCTOR INC.
3-23
QS7203, QS7204
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V.
DC Output Voltage V0 -0.5V to Vcc + 0.5V.
DC Input Voltage V( -0.5V to Vqc + 0-5V-
AC Input Voltage (for pulse width<20 ns) -3.0 V.
DC Input Diode Current with V|<0 - -20 mA.
DC Input Diode Current with V | >Vqq 20 mA.
DC Output Diode Current with Vq <0 -50 mA.
DC Output Diode Current with Vq >V cc 50 mfil-
DC Output Current Max. sink current/pin 70 mA.
DC Output Current Max. source current/pin 30 mA.
Total DC Ground Current (NxlOL +MxAI CC) mA.
Total DC VCC Power Supply Current (NxlOH + MxAl CC) mA.
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts.
TSTG Storage Temperature -65° to +165°C.
CAPACITANCE
Ta = 25 °C, f = 1 mUz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V
5
8
PF
Cout
Output Capacitance
Vout = 0 V
5
8
PF
Note: Capacitance is guaranteed but not tested
■
■
■
-
s
3-24
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
=====
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±1 0% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.0
6.0
2.2
6.0
VOltS
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -2 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc=MIN
0.4
0.4
| Hi |
Input Leakage
Vcc = MAX,
Vin = GND to Vcc
1
10
uA
| lb |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
10
10
Notes:
Trans ent inputs with Vil not more negative than -1 .5 volts are permitted for pulse widths < 1 0 ns
POWER SUPPLY CHARACTERISTICS
Commercial TA=0°C to 70°C, Vcc=5 0V±1 0% Military TA=-55°C to 1 25°C, Vcc=5 0V±1 0%
Vic = 0.2 Volts, Vhc = Vcc - 0.2 Volts
Symbol
Parameter
<35
>50
Unit
C
M
C
M
Icc1
Operating OperatingCurrent
Vcc = MAX, Outputs open
100
120
100
120
mA
ICC2
Standby Current
R = W = RS = FL/RT = Vih
15
20
8
15
Isb
Power Down Current
5
9
5
9
All Inputs at Vhc or Vic
R = W=RS=FI7RT = Vhc
QUALITY SEMICONDUCTOR INC.
3-25
QS7203, QS7204
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V±10%, TA=0°C to +70°C, MILITARY VCC=5V±10%, TA=-55°C to +125°C
-80
-120
Unit
Type
Symbol
Parameter (1)
Note
-15
-20
-25
-35
-50
READ CYCLE
f RF
Read Frequency.MHz
2
40
33
28
22
15
10
7
MHz
Min
tRC
Read Cycle Time
25
30
45
65
35
100
140
ns
35
120
tA
Read Access Time
15
20
25
50
80
Max
t RR
Read Recovery Time
10
10
10
10
15
20
20
Min
Read Pulse Width
1
15
20
25
35
50
80
120
tRPW
t RLZ
TTbata Bus Low Z
2
3
3
3
3
3
3
3
tWLZ
W Data Bus LowZ
2,3
3
3
3
3
3
3
3
tDV
TThigh to Data Hold Time
3
3
3
3
3
3
3
t RHZ
TTto Data High Z
14
18
18
20
30
35
35
WRITE CYCLE
fWF
Write Frequency, MHz
2
40
33
28
22
15
10
7
MHz
Min
two
Write Cycle Time
25
30
35
45
65
100
140
ns
tWPW
Write Pulse Width
1
15
20
25
35
50
80
120
tWR
Write Recovery Time
10
10
10
10
15
20
20
tDS
Write Data Setup Time
8
12
15
18
30
40
40
tDH
Write Data Hold Time
0
0
0
0
0
0
0
RESET AND RETRANSMIT CYCLES
tRSC
Reset Cycle Time
25
30
35
45
65
100
140
ns
Min
tRS
Reset Pulse Width
1
15
20
25
35
50
80
120
tRSS
Reset Setup Time
15
20
25
35
50
80
120
t RSR
Reset Recovery Time
10
10
10
10
15
20
20
t RTC
Retransmit Cycle Time
25
30
35
45
65
100
140
t RT
Retransmit Pulse Width
1
15
20
25
35
50
80
120
t RTS
Retransmit Setup Time
2
15
20
25
35
50
80
120
t RTR
Retransmit Recovery
10
10
10
10
15
20
20
Notes: These timings are measured as defined in AC Test Conditions
1 . Pulse widths less than the specified minimum value may upset the internal pointers and are not allowed.
2. These values are guaranteed by design and not tested
3. This applies to the read data flow-through mode only.
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
Symbol
Parameter (1)
Note
-15
-20
-25
-35
-50 I -80
-120
Unit
Type
FLAG TIMING
tREF
Read Low to EF Low
15
20
25
30
45
60
60
ns
Max
t RFF
Read High to FF High
15
20
25
30
45
60
60
t RHF
Read High to HF High
15
20
25
35
45
60
60
tWEF
Write High to EF High
15
20
25
30
45
60
60
tWFF
Write Low to FF Low
15
20
25
30
45
60
60
tWHF
Write Low to HF Low
15
20
25
35
45
60
60
t EFL
Reset to EF High
15
20
25
35
45
60
60
t FFH
Reset to FF Low
15
20
25
35
45
60
60
t HFH
Reset to HF Low
15
20
25
35
45
60
60
EXPANSION TIMING
tXOL
Read/Write to XO Low
15
20
25
35
50
80
120
ns
Max
tXOH
Read/Write to XO High
15
20
25
35
50
80
120
txi
XI Pulse Width
15
20
25
35
50
80
120
tXIR
XI Recovery Time
10
10
10
10
10
10
10
Min
txis
XI Setup Time
10
15
15
15
15
15
15
AC TEST CONDITIONS
+5V
1.1K Q
To Output Pin q
680 CI
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
GND to 3.0V
3 ns
1.5V
1.5V
^30PP*^anrdSC°Pe
\7
—
QUALITY SEMICONDUCTOR INC. 3-27
QS7203, QS7204
TIMING DIAGRAMS
lRC
t
RLZ
w
D0-°8
RPW
RR
+ xdv^z n A
Asynchronous Read and Write Operations
RS
W
EF
HF.FF
1
tRS
tRSS,^
JJ
t RSS +
— ►
[RSC
RSR
fl 1 1 1 1 1 1 1 ITTT\
1 EFL
minmiuzj
Notes: Read and Write have to be at a HIGH level around the rising edge of Reset. The flags may change during
reset but are valid at t RSC.
Reset Timing
3-28
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
FF
WFF
A V
^ RFF
Full Flag Behavior from Last Write to First Read
_ ,
' RFF
tWPF=tWpw
Full Flag and Required Write Pulse at Full Condition
Empty Flag Behavior from Last Read to First Write
3-29
QS7203, QS7204
W
EF
WEF
* — ►
t -t
lRPE =t RPW
Empty Flag and Required Pulse Width at Empty Condition
■
HALF FULL(OR
<HALF FULL)
W
R
HF1
J — \
t
WHF
MORE THAN
HALF FULL
HALF
— \ /
3;
THIS EDGE CAUS
THE FIFO TO BE HALF FULL,
BUT THE FLAG IS ASSERTED
AT A FIFO DEPTH OF >HALF FULL
RHF
FULL
FULL
Half Full Flag Timings
RT
R,W
f —
' RT
►
\
f )
4 ►
1 RTF
i
/ / // \
/ tRTS
* — H
}
FF.EF.HF
////// 7~yz
VALID FLAGS
Note: The flags may change during retransmit but will be valid at t RTC
Retransmit Function Timing
3-30
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
=
WRITE or READ TO LAST PHYSICAL WRITE or READ TO FIRST
LOCATION OF DEVICE 1
W /R
\ \
' \
1 XOL
tX0H
XGT(XT2)
PHYSICAL LOCATION OF DEVICE 2
/
Note: The Expansion Out of Device 1,"XfJT"is connected to the E
Expansion Out Timing
In of Device 2, XI2
READ FROM FIRST
PHYSICAL LOCATION
Expansion In Timing
-
QUALITY SEMICONDUCTOR INC.
3-31
QS7203, QS7204
DATA IN X~
w
r m
DATA OUT
R
W
FF
DATA IN
DATA OUT
t WEF
WLZ
t RPE
1
t REF
< ►
Data Flow-through Mode
A.
i
I
tRFF
t WPF
* — y — 3 ^ff
tDS h-H^-^to
Write Data Flow-through Mode
3-32
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
OPERATIONAL DESCRIPTION AND APPLICATION INFORMATION
The QS7201 through QS7204 are 512x9 through 4Kx9 FIFOs respectively. These FIFOs use a dual-port
RAM based architecture and having independent read and write pointers. This allows high speed and
zero fall-through time. The Write line causes data to be written into the FIFO. The Read line causes data
to be read from the FIFO. The Read line also activates the three-state outputs to present the read data.
The read and write pointers are incremented on the rising edges of the Read and Write lines. The flag
circuitry is based on a reliable sequential design giving precise half full, full, and empty conditions. These
flags also prevent the FIFO from being written into when full or being read from when empty. Depth
expansion pins are provided which allow these FIFOs to be expanded in depth without speed penalty.
Retransmit capability is provided. Activating the Retransmit pin resets the read pointer to zero, and is
useful for data communications and digital filtering applications.
SIGNAL DESCRIPTION
PATA INPUTS
D0-D8
The Data In lines D0 to Ds provide data to be written into the FIFO. Note: unused inputs must be tied to
Vcc or Gnd.
CONTROL INPUTS
Reset (R~S)
The Reset input resets the Read and Write pointers and the flags to zero. The FIFO must be reset at
power-up to insure proper operation of the pointers and flags. This is done by asserting the Reset line to
a LOW state, which causes the FIFO flags to be set to empty. This causes the Empty flag is asserted and
the Full and Half Full flags to be deasserted. Read and Write lines must be HIGH for t RSS before and
t RSR after the rising edge of the Reset signal for a valid reset operation.
Write (W)
The Write line caused data to be written into the FIFO. A write cycle is initiated by the falling edge of the
Write signal. A write will occur if the full flag was not asserted, indicative of at least one empty location in
the FIFO. Data is stored in the FIFO on the rising edge of the Write signal using the data set-up and hold
times specified. Data is stored in a sequential manner in the FIFO, and the read and write operations can
be asynchronous. The falling edge of the Write signal asserts the Half full and Full flags when the next
word after half full is written and when the last word has been written, respectively. The rising edge of the
Write line deasserts the empty flag when the first write is performed after an empty or reset condition.
When the Full flag is asserted, subsequent writes are blocked. The user can apply a write pulse after the
full condition is deasserted.
Read (R)
The Read signal causes data to be read from the FIFO. A read cycle is initiated by the falling edge of the
Read signal. A read is performed if the empty flag is not asserted, indicative of at least one word being
present in the FIFO. The data is accessed in a First-In-First-Out basis asynchronous to the Write
operations. After the Read control is deasserted the data outputs go from a valid state into high-
impedance. The outputs remain in high-impedance until the next read cycle. When all the data is read on
the last read cycle, the Empty flag is asserted, and will inhibit any subsequent reads. The outputs will be in
high-impedance for subsequent read operation until a write occurs that deasserts the Empty flag, allowing
a read cycle to begin. The outputs may also be in high impedance when the FIFOs are cascaded in depth.
In this case, only the active FIFO asserts data , and the other FIFOs data outputs are in high-impedance.
The falling edge of the read signal will set the Empty Flag during the read of the last word in the FIFO. The
rising edge of the Read signal will deassert the Half Full and the Full flags when the FIFO has reached half
full and when the FIFO was full, respectively.
QUALITY SEMICONDUCTOR INC. 3-33
QS7203, QS7204
First Load/ Retransmit (FL7RT)
This is a dual purpose input. In the depth expansion mode, this pin indicates the first FIFO device that will
be loaded or read from after a reset operation. In the standalone or width expansion mode (when the the
expansion input is grounded) this pin initiates the a retransmit function.
Retransmit resets the read pointer to zero. The Read and Write signals must be HIGH before and after the
rising edge of the retransmit pulse. The retransmit feature is useful when the same data needs to be read
again without rewriting it into the FIFO. Pulsing retransmit pin will cause the read pointer to be reset
zero and the previously read data can be read again. The flags will change according to the relati
location of the pointers after the retransmit pulse.
Expansion In (XT)
This is a dual purpose pin. When it is grounded then it indicates that the FIFO is a standalone device.
When it is not grounded, it indicates that the FIFO is in the depth expansion mode. In the depth
expansion mode this pin is connected to the XO" pin of the previous device.
DATA OUTPUTS
Data Outputs Qn-Qs
The 9-bit data output bus, Qq-Qq receives the read data from the FIFO. It is active whenever the Read
signal is low. It is in a high impedance state when the Read signal is high. It is also in high impedance
when the FIFO Empty flag is active (i.e., when the FIFO is empty).
CONTROL OUTPUTS
Full Flag (FF)
The Full Flag indicates that the FIFO is full. The Full Flag is asserted when there is only one empty location
in the FIFO and a falling edge of the Write signal initiates the last write operation. The rising edge of the
Read signal deasserts the flag, as at least one location has become available.
Empty Flag (EF)
The Empty Flag indicates the FIFO is empty. It is asserted when there is only one word in the FIFO, and a
falling edge of the Read signal initiates the last read operation. The rising edge of the write signal
deasserts the flag, as one word is now present in the FIFO.
Expansion Out/Half Full flag (X07HF)
This is a dual purpose flag. In the single device mode, the Expansion In is grounded and the Half Full flag
output is present on this pin. Whenever the FIFO is more than half full the flag remains asserted . When
the FIFO is exactly half full and the next falling edge of the Write signal asserts the flag. The rising edge of
read that causes the FIFO to be half full, will deassert the half full flag. It will remain asserted until the FIFO
is half full or less than half full. The name given to the flag is half full, I
I, but it is asserted on the one
half full condition.
In the depth expansion mode, the Expansion Out is connected to the Expansion In of the next device.
This causes the next device to perform write or read operations.
■
■ '
3-34
QUALITY SEMICONDUCTOR INC.
QS7203, QS7204
OPERATING MODES
SINGLE DEVICE MODE
A FIFO Is in standalone mode when the Expansion In control is grounded. In this mode the half full flag is
available on the shared X07HF line. Figure 1 shows the standalone mode and this applies to FIFO width
expansion, as shown in figure 2.
■
DEPTH EXPANSION MODE
A FIFO is in the depth expansion mode when the Expansion In control is not grounded but tied to the
Expansion Out pin of the previous FIFO. Using the depth expansion mode, the 7201/02 can be easily
cascaded to create FIFOs of larger depth. The devices are cascaded as shown in figure 3. In the depth
expansion mode, the device that receives the first word of data has its First Load input grounded. The
other devices have their First Load inputs in the high state. Two 4-input OR gates are required to create
the composite Full and Empty flags for the FIFO array. In using the depth expansion mode, care must be
taken to keep the traces short between the Expansion In of one device to the Expansion Out of the next
device to minimize crosstalk noise.
FLOW-THROUGH MODES
Flow-through modes refer to the internal operation of the FIFO in empty and full conditions. Flow through
modes allow data to flow directly through the FIFO from input to output under the appropriate empty and
full conditions.
Two types of flow-through modes, a read flow-through and a write flow-through, are supported by the
FIFO. In the read flow-through mode the FIFO is empty, and the read side is waiting for data from a write.
Read flow-through is represented by an empty FIFO that has its Read line held low, and a write occurs.
This rising edge of the Write would deassert the Empty flag and cause valid data to appear on the outputs
after a certain time delay of t wef + 1 A- The Read line being low would cause the data to be read and also
assert the empty flag once again. The user must raise the Read line in order to increment the read
pointer.
In the write flow-through mode, the FIFO is full and the write side is waiting for a word location to be made
available by a read. A write flow-through operation permits the writing of a single word of data immediately
after reading one word of of data from a full FIFO. This is similar to the read flow-through case, and the
Write line must toggled to increment the write pointer.
■
QUALITY SEMICONDUCTOR INC.
3-35
QS7203, QS7204
■
Data In 0-8
Write Clock
Reset
Full Flag
D0-D8 Q0-Q8
W 720X R
R5 FIF0 RT
FF
XI
EF
HF
^7
Data Out 0-8
Read Clock
Retransmit
Empty Flag
Half Full Flag
Figure 1. The FIFO in a Standalone Mode
Data In 0-8
Write Clock
Reset
Data In 9-17
Full Flag <4-
FF
XT
EF
HF
Data Out 0-8
Data Out 9-17
Empty Flag
Half Full Flag
Figure 2. A 18-bit wide FIFO using 2 FIFOs
3-36
QUALITY SEMICONDUCTOR INC.
w
Data In
^9
R5
XI
w
FIT
R
Vcc
4—
FF
R5 EF
Xo
Vcc
XI
FL
R
7203/4
FF
R5 EF
Xo
Vcc
XI
w
FC
R
7203/4
FF
RS EF
Xo
Vcc
XI FC
W
7203/4
FF
RS
Xo
EF
R
Data Out
CEF
Note that the composite Empty Flag and Full flag requires the OR-ing of the individual Empty and Full flags,
respectively.
Figure 3. Building a 4N-deep FIFO using Four N-deep FIFOs
\ INC.
QS7203, QS7204
— **s
■
QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
Q
512x9: QS7211
1Kx9: QS7212
High Speed CMOS
9-bit FIFO
with Output Enable
FEATURES/BENEFITS
• 1 5 ns flag and data access times • 40 MHz cycle time
• Separate Output Enable and Read Clock • Output latch holds data while Read Clock high
• Fully Asynchronous Read and Write • TTL input and output level compatible
• Zero fall-through time • Available in 28-pin 300 mil PDIP,
• Dual Port RAM-based cell using 6T technology SOIC, and SOJ
DESCRIPTION
The QS8211 and QS8212 are 512x9 and 1Kx9 FIFOs respectively with output enable and output
latch. These FIFOs use a dual-port RAM based architecture and having independent read and write
pointers. This allows high speed and zero fall-through time. The read and write pointers are
incremented on the rising edges of the Read and Write lines. The flag circuitry is based on a reliable
sequential design giving precise half-full, full, and empty conditions. These flags also prevent the FIFO
from being written into when full or being read from when empty. Retransmit capability is provided.
Retransmits resets the read pointer to zero, and is useful for data communications and digital filtering
applications. Separate Output Enable and Read clock inputs are provided, and an output latch is
provided to hold data when the read clock is high, allowing these FIFOs to be used in bus applications.
FUNCTIONAL BLOCK DIAGRAM
W
R
RT
0"E
WRITE
CONTROL
READ
CONTROL
RESET &
RETRANSMIT
LOGIC
WRITE
POINTER
READ
POINTER
DATA IN
D0-D8
I
t
DUAL PORT
RAM ARRAY
512.1KX9
FLAG
LOGIC
EF
FF
HF
LATCH
DATA OUT
Q0-Q8
■
QUALITY SEMICONDUCTOR INC.
3-39
QS7211, QS7212
—
PINOUTS
28 □ VCC
27 ^ D4
26 □ D5
25 □ D6
24 □ D7
23 □ RT
22 □ R5
21 □ EF
20 □TT
19 □ Q7
18 □ Q6
17 □ Q5
16 □ Q4
ALL PINS TOP VIEW
PIN DESCRIPTIONS
Name
I/O
Description
Di
I
Data Inputs
Qi
O
Data Outputs
H
Read Clock
W
Write Clock
Output Enable
ffS
Reset
RT
Retransmit
EF
0
Empty Flag
FF
0
Full Flag
HF
0
Half Full Flag
3-40
QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
FUNCTION TABLE
Mode
Inputs
Internal
Status
Outputs
RT
w
R
Read
Pointer
Write
Pointer
Read
Latch
EF
HF
FF
0.1
Reset
L
x
H
H
x
Zero
Zero
x
L
H
H
x
Re-
transmit
H
L
X
H
X
Location
Zero
_
X
(3)
(3)
(3)
X
Write
H
H
T
H
X
Increment
(2)
Q(i)
(3)
(3)
(3)
X
Read
H
H
H
4
L
Incre-
ment (1)
Q(i)
(3)
(3)
(3)
Q(i)
Hold
H
H
H
H
L
Q(i+1)
Q(i)
(3)
(3)
(3)
0.(0
Next Data
H
H
H
L
L
Q(i+2)
0(1+1)
(3)
(3)
(3)
0(1+1)
Disable
H
H
H
L
H
I — ; — I
m
(3)
(3)
(3)
Hi-Z
1 1
Notes:
(1) The Read Pointer will increment if the FIFO is not empty.
(2) The Write flag will increment if the FIFO is not full.
(3) The flags will reflect the relative locations of the read and write pointers.
QS7211, QS7212
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to Vcc + 0.5V
DC Input Voltage V( -0.5V to Vcc + 0.5V
AC Input Voltage (for pulse width<20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA.
DC Input Diode Current with V | >Vqq 20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Diode Current with Vq >V cc 50 mA
DC Output Current Max. sink current/pin 70 mA
DC Output Current Max. source current/pin 30 mA
Total DC Ground Current (NxlOL +MxAI CC) mA
Total DC VCC Power Supply Current (NxlOH + MxAl CC) mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTG Storage Temperature -65° to +165°C
CAPACITANCE
Ta = 25°C, f = 1 mHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V
5
8
PF
Cout
Output Capacitance
Vout = 0 V
5
8
PF
Note: Capacitance is guaranteed but not tested
3-42
QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCc=5 0V±1 0% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
1 '1
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.0
6.0
2.2
6.0
Volts
Vil
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -2 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc=MIN
0.4
0.4
|l|
input Leakage
Vcc = MAX,
Vin = GND to Vcc
1
10
HA
1 «o |
Output Leakage
Vcc = MAX,
Vout = GND to Vcc
10
10
Notes:
1. Transient inputs with Vil not more negative than -1.5 volts are permitted for pulse widths < 10 ns
POWER SUPPLY CHARACTERISTICS
Commercial TA=0°C to 70°C, VCC=5.0V±1 0% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Vic = 0.2 Volts, Vhc = Vcc - 0.2 Volts
Symbol
Parameter
<35
>50
Unit
C
M
C
M
Icc1
Operating OperatingCurrent
Vcc = MAX, Outputs open
100
120
100
120
mA
Icc2
Standby Current
R = W = RS=FL/RT = Vih
15
20
8
15
Isb
Power Down Current
All Inputs at Vhc or Vic
5
9
5
9
R = W = RS = FL/RT = Vhc
-
QUALITY SEMICONDUCTOR INC.
3-43
QS7211, QS7212
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
For 15 ns Commercial, 20,25,35,50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V±1 0%, TA=0°C to +70°C, MILITARY VCC=5V±10%, TA=-55°C to +125°C
Symbol
Parameter (1)
Note
- 1 5
-20
-25
-35
Unit
TvnA
READ CYCLE
f RF
Read Frequency, mHz
2
40
28
22
mHz
Min
tRC
Read Cycle Time
^n
4*5
■ Id
tA
Read Access Time
15
20
25
35
Max
t RR
Read Recovery Time
10
10
10
10
Min
tRPW
Read Pulse Width
1
15
20
25
35
tOE
TJEto Data Low Z
2
3
3
3
3
Min
6
6.5
7
8
Max
toz
TSFto Data High Z
2
3
3
3
3
Min
14
18
18
20
Max
WRITE CYCLE
fWF
Write Frequency, mHz
2
40
33
28
22
mHz
Min
twc
Write Cycle Time
25
30
35
45
ns
tWPW
Write Pulse Width
1
15
20
25
35
tWR
Write Recovery Time
10
10
10
10
tDS
Write Data Setup Time
8
12
15
18
tDH
Write Data Hold Time
0
0
0
0
RESET CYCLE
tRSC
Reset Cycle Time
25
30
35
45
ns
Min
tRS
Reset Pulse Width
1
15
20
_ _
tRSS
Reset Setup Time
15
20
25
35
tRSR
Reset Recovery Time
10
10
10
10
t RTC
Retransmit Cycle Time
25
30
35
45
t RT
Retransmit Pulse Width
1
15
20
25
35
t RTS
Retransmit Setup Time
2
15
20
25
35
t RTR
Retransmit Recovery
10
10
10
10
Notes: These timings are measured as defined in AC Test Conditions
1 . Pulse widths less than the specified minimum value may upset the internal pointers and are not allowed.
2. These values are guaranteed by design and not tested
3. This applies to the read data flow-through mode only.
3-44 QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V±10%, TA=0°Cto +70°C, MILITARY VCC=5V±10%, TA=-55°C to +125°C
Symbol
Parameter (1)
Note
-15
-20
-25
-35
Unit
Type
FLAG TIMING
tREF
Read Low to EF Low
15
20
25
30
ns
Max
t RFF
Read High to FF High
15
20
25
30
t RHF
Read High to HF High
15
20
25
35
tWEF
Write High to EF High
15
20
25
30
tWFF
Write Low to FF Low
15
20
25
30
tWHF
Write Low to HF Low
15
20
25
35
t EFL
Reset to EF High
15
20
25
35
t FFH
Reset to FF Low
15
20
25
35
t HFH
Reset to HF Low
15
20
25
35
AC TEST CONDITIONS
+5V
To Output Pin q
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
30 pF* * Includes jig and scope
QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
TIMING DIAGRAMS
< tRC ►
OE
lRPW
RR
■w »
WPW
wc
DS
^ t WR \
loz
•4— ►
>
^ VALID O/Py
' — —
DH
RS '
W
EF
HF.FF
Asynchronous Read and Write Operations
tRS
tRSS^-
ZT
tRSSrt-
£U7
RSC
—
lRSR
-
_
m II II II ITTTX
EFL
v in n ii m
^fh-'ffh
Notes: Read and Write have to be at a HIGH level around the rising edge of Reset. The flags may change during
reset but are valid at t RSC.
Reset Timing
3-46
QUALITY
TOR INC.
QS7211, QS7212
FT
W"
WFF
\ r\ r
\
" 1 RFF
Full Flag Behavior from Last Write to First Read
R
FF
w~
tWPF=twpw
Full Flag and Required Write Pulse at Full Condition
W
R"
LAST READ
READ
INHIBITED
FIRST WRITE
\J
lWEF
ANOTHER
READ
Empty Flag Behavior from Last Read to First Write
QUALITY
:tor inc.
3-47
QS7211, QS7212
W
EF
R"
1 WEF
lRPE =t RPW
% U LRPI
\ \ v \ v v \ \-YY\yr~
Empty Flag and Required Pulse Width at Empty Condition
HALF FULL(OR
<HALF FULL)
w {
MORE THAN
HALF FULL
HALF . >HALF
FULL FULL
R —
l_ip
/ \ /
■ ^ — — »
ir *WHF «
THIS EDGE CAUSES
THE FIFO TO BE HALF FULL,
BUT THE FLAG IS ASSERTED
AT A FIFO DEPTH OF >HALF FULL
Half Full Flag Timings
RT
n i \j
>
^ — i
/
* — » 1
/ / / / \
/ lRTS
< — H
\
RTR
FF.EF.HF
/////// ^^FU^QS
Retransmit Function Timing
3-48
QUALITY
QS7211, QS7212
DATA IN
W ■
X
[WEF
WLZ
DATA OUT
RPE
•4 ►
<« ►
r/////// y rX>^ C °'p VALID
■
1 A
* OE = Low
Read Data Flow-through Mode
W
FF
DATA IN
RFF
WPF
•4 t
DS
+ ►
mz y / y y y y*»» ™y/////77
lDV
•4— ►
WFF
>-
Low
Write Data Flow-through Mode
■
INC.
3-49
QS7211, QS7212
OPERATIONAL DESCRIPTION AND APPLICATION INFORMATION
The QS821 1 through QS8214 are 512x9 through 4Kx9 FIFOs respectively with output enable and latch.
These FIFOs use a dual-port RAM based architecture and having independent read and write pointers.
This allows high speed and zero fall-through time. The Write line causes data to be written into the FIFO.
The Read line causes data to be read from the FIFO. The Ouput Enable line activates the three-state
outputs to present the read data. An internal latch is provided to hold the read data while the Read line is
high. The read and write pointers are incremented on the rising edges of the Read and Write lines. The
flag circuitry is based on a reliable sequential design giving precise half full, full, and empty conditions.
These flags also prevent the FIFO from being written into when full or being read from when empty.
Retransmit capability is provided. Activating the Retransmit pin resets the read pointer to zero, and is
useful for data communications and digital filtering applications.
SIGNAL DESCRIPTION
PATA INPUTS
D0-D8
The Data In lines D0 to D8 provide data to be written into the FIFO. Note: unused inputs must be tied to
Vcc or Gnd.
CONTROL INPUTS
Reset (R~5)
The Reset input resets the Read and Write pointers and the flags to zero. The FIFO must be reset at
power-up to insure proper operation of the pointers and flags. This is done by asserting the Reset line to
a LOW state, which causes the FIFO flags to be set to empty. This causes the Empty flag is asserted and
the Full and Half Full flags to be deasserted. Read and Write lines must be HIGH for t RSS before and
t RSR after the rising edge of the Reset signal for a valid reset operation.
Write (W)
The Write line caused data to be written into the FIFO. A write cycle is initiated by the falling edge of the
Write signal. A write will occur if the full flag was not asserted, indicative of at least one empty location in
the FIFO. Data is stored in the FIFO on the rising edge of the Write signal using the data set-up and hold
times specified. Data is stored in a sequential manner in the FIFO, and the read and write operations can
be asynchronous. The falling edge of the Write signal asserts the Half full and Full flags when the next
word after half full is written and when the last word has been written, respectively. The rising edge of the
Write line deasserts the empty flag when the first write is performed after an empty or reset condition.
When the Full flag is asserted, subsequent writes are blocked. The user can apply a write pulse after the
full condition is deasserted.
Read (R~)
The Read signal causes data to be read from the FIFO. A read cycle is initiated by the falling edge of the
Read signal. A read is performed if the empty flag is not asserted, indicative of at least one word being
present in the FIFO. The data is accessed in a First-In-First-Out basis asynchronous to the Write
operations. When all the data is read on the last read cycle, the Empty flag is asserted, and will inhibit any
subsequent reads. The falling edge of the read signal will set the Empty Flag during the read of the last
word in the FIFO. The rising edge of the Read signal will deassert the Half Full and the Full flags when the
FIFO has reached half full and when the FIFO was full, respectively.
Output Enable (0~E)
The Output Enable pin activates the output drivers. It is independent of the Read clock. A latch is
provided which is driven by the Read clock. This latch holds the current value of the read data when the
Read clock goes high. The read latch maintains the current data value while the next value is being
accessed. This allows the FIFO to drive data to a bus while the Read clock is high and the next location is
3-50 QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
=====
being accessed. If the read clock high time is <
only on the falling edge of the Read clock.
Retransmit (RT)
This pin initiates the a retransmit function. Retransmit resets the read pointer to zero. The Read and Write
signals must be HIGH before and after the rising edge of the retransmit pulse. The retransmit feature is
useful when the same data needs to be read again without rewriting it into the FIFO. Pulsing retransmit pin
will cause the read pointer to be reset to zero and the previously read data can be read again. The flags
will change according to the relative location of the pointers after the retransmit pulse.
'
DATA OUTPUTS
■
Data Outputs Q0-Q8
The 9-bit data output bus, Qrj-Qs receives the read data from the FIFO. It is active whenever the Read
signal is low. It is in a high impedance state when the Read signal is high. It is also in high impedance
when the FIFO Empty flag is active (i.e., when the FIFO is empty).
CONTROL OUTPUTS
Full Flag (FF)
The Full Flag indicates that the FIFO is full. The Full Flag is asserted when there is only one empty location
in the FIFO and a falling edge of the Write signal initiates the last write operation. The rising edge of the
Read signal deasserts the flag, as at least one location has become available.
Empty Flag (EF)
The Empty Flag indicates the FIFO is empty. It is asserted when there is only one word in the FIFO, and a
falling edge of the Read signal initiates the last read operation. The rising edge of the write signal
deasserts the flag, as one word is now present in the FIFO.
Half Full flag (HF)
Whenever the FIFO is more than half full the Half Full flag remains asserted . When the FIFO is exactly half
full, the next falling edge of the Write signal asserts the flag. The rising edge of read that causes the
FIFO to be half full, will deassert the half full flag. It will remain asserted until the FIFO is half full or less than
half full. The name given to the flag is half full, but it is asserted on the one plus the half full condition.
QUALITY SEMICONDUCTOR INC.
QS7211, QS7212
OPERATING MODES
FLOW-THROUGH MODES
Row-through modes refer to the internal operation of the FIFO in empty and full conditions. Flow through
modes allow data to flow directly through the FIFO from input to output under the appropriate empty and
Two types of flow-through modes, a read flow-through and a write flow-through, are supported by the
FIFO. In the read flow-through mode the FIFO is empty, and the read side is waiting for data from a write.
Read flow-through is represented by an empty FIFO that has its Read line held low, and a write occurs.
This rising edge of the Write would deassert the Empty flag and cause valid data to appear on the outputs
after a certain time delay of t wef + 1 A- Tne Read line ^ing low would cause the data to be read and also
assert the empty flag once again. The user must raise the Read line in order to increment the read
pointer.
In the write flow-through mode, the FIFO is full and the write side is waiting for a word location to be made
available by a read. A write flow-through operation permits the writing of a single word of data immediately
after reading one word of of data from a full FIFO. This is similar to the read flow-through case, and the
Write line must toggled to increment the write pointer.
■
-
■
3-52 QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
Q
High Speed CMOS
9-bit Clocked FIFO
2Kx9: QS7223
4Kx9: QS7224
ADVANCE
INFORMATION
FEATURES/BENEFITS
■ Clocked interface FIFOs for high speed systems
• Data and flags change on rising edge of clocks
■ Fully Asynchronous Read and Write
• TTL input and output level compatible
• Dual Port RAM-based cell using 6T technology
■ 40 MHz cycle time with symmetrical clocks
> Depth expansion without additional logic or pins
■ Register-like: outputs show current word in FIFO
• Available in 28-pin 300 mil PDIP,
SOIC, and SOJ
DESCRIPTION
The QS7223 and QS7224 are 2Kx9 and 4Kx9 FIFOs respectively with clocked interfaces for both read
and write. These interfaces provide high speed data buffering in system designs and allow symmetrical
clocks at speeds to 40 mHz. Free running independent read and write clocks are controlled by read and
write enable lines. All signals are relative to the rising edges of the clocks. Write enable and write data are
accepted at the rising edge and the full flag and the half full flag change after the rising edge of the write
clock. Read enable is accepted at the rising edge and read data and the full flag changesafter the rising
edge of the read clock. These FIFOs use a dual-port RAM based architecture and having independent
read and write pointers. The read and write pointers are set to zero by the reset pulse. A Write Enable
causes data to be written and the write pointer to be incremented by the rising edge of the write clock. If
the FIFO was empty, the write data will be present at the read outputs, and the empty flag will be cleared
at the next rising edge of the read clock. A Read Enable will cause the read pointer to be incremented to
the next word on the rising edge of the read clock. If there was only one word in the FIFO, the empty flag
will be set by this same rising edge. The flag circuitry is based on a reliable sequential design giving
precise half-full, full, and empty conditions. These flags also prevent the FIFO from being written into
when full or being read from when empty.
FUNCTIONAL BLOCK DIAGRAM
WE
WCLK
RE
WRITE
CONTROL
READ
Rm*-»l CONTROL
R5
RESET
LOGIC
WRITE
POINTER
READ
POINTER
IN
D0^D8
DUAL PORT
RAM ARRAY
2Kx9, 4Kx9
FLAG
LOGIC
T
EFR
FFR
HFR
DATA OUT
Q0-Q8
QS7223, QS7224
PINOUTS
■
PIN DESCRIPTIONS
Name
I/O
Description
Di
1
Data Inputs
Qi
0
Data Outputs
RC
Read Clock
RE
Read Enable
wc
Write Clock
WE
Write Enable
E3
Reset
EFR
0
Empty Flag
FFR
0
Full Flag
HFR
0
Half Full Flag
i
3-54
QUALITY
QS7223, QS7224
FUNCTION TABLE
MODE
Inputs
Internal Status
Outputs (After Clock)
ET>
WE
WC
RE
RC
Write
Pointer
Read
Pointer
EFR
FFR
HFR
Ql
Read/Write Controls
Reset
L
X
X
X
X
0000
0000
H
L
L
O(0)
Write
H
L
T
X
X
YY+1
XX
(3)
(3)
(3)
Q(XX)
Read
H
X
X
L
T
YY
XX+1
(3)
(3)
(3)
Q(XX+1)
Hold
H
H
T
H
T
YY
XX
(3)
(3)
(3)
Q(XX)
Read/Write at Empty
Reset
L
X
X
X
X
0000
0000
H
L
L
O(0)
1st Write
H
L
t
H
X
0001
0000
L
L
L
O(0)
2nd Write
H
L
T
H
X
0002
0000
L
L
L
O(0)
1st Read
H
H
X
L
T
0002
0001
L
L
L
0(1)
2nd Read
H
H
X
L
T
0002
0002
H
-
L
0(2)
Read/Write at Full
Last Write
H
L
T
H
X
1000
0000
L
H
H
O(0)
1st Read @ Full
H
H
X
L
T
1000
0001
L
L
H
Q(1)
Read/Write at Half Full
2048th Write
H
L
T
X
X
0800
0000
L
L
L
O(0)
2048th+1 Write
H
L
t
X
X
0801
0000
L
L
H
O(0)
1st Read @ HF
H
H
X
L
T
0801
0001
L
L
L
0(1)
Notes:
(1) The Read Pointer will increment if the FIFO is not empty.
(2) The Write flag will increment if the FIFO is not full.
(3) The flags will reflect the relative locations of the read and write pointers.
QUALITY SEMICONDUCTOR INC.
3-55
QS7223, QS7224
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to Vqc + 0.5V
DC Input Voltage V, -0.5V to Vcc + 0.5V
AC Input Voltage (for pulse width<20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Input Diode Current with V | >Vqq 20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Diode Current with Vq >V cc 50 mA
DC Output Current Max. sink current/pin 70 mA
DC Output Current Max. source current/pin 30 mA
Total DC Ground Current (NxlOL +MxAI CC) mA
Total DC VCC Power Supply Current (NxlOH + MxAl CC) mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTG Storage Temperature -65° to +165°C
CAPACITANCE
Ta = 25°C, f=1 mHz
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance
Vin = 0 V
5
8
PF
Note: Capacitance is guaranteed but not tested
3-56
QUALITY SEMICONDUCTOR INC.
DC ELECTRICAL I
Commercial TA=0°C to 70°C, Vcc=50V±10%
OVER OPERATING RANGE
Military TA=-55°C to 125°C, VCC=5.0V±10%
Symbol
Parameter
Test Conditions
Commercial
Military
Unit
Min
Max
Min
Max
Vih
Input HIGH Voltage
Logic High for All Inputs
2.0
6.0
2.2
6.0
Volts
Vi,
Input LOW Voltage (1)
Logic Low for All Inputs
0.8
0.8
Voh
Output HIGH Voltage
loh = -2 mA, Vcc = MIN
2.4
2.4
Vol
Output LOW Voltage
lol = 8mA,Vcc = MIN
0.4
0.4
l4
Input Leakaae
Vcc = MAX,
5
10
HA
Vin = GND to Vcc
Notes
1.
nt inputs with Vil not more negative than -1 .5 volts are permitted I
POWER SUPPLY CHARACTERISTICS
Commercial TA=0°C to 70°C, VCC=5.0V±1 0% Military TA=-55°C to 1 25°C, Vcc=5.
Vic = 0.2 Volts, Vhc = Vcc - 0.2 Volts
Symbol
Parameter
Clock Rate, mHz
Unit
40
33
25
20
Icc1
Operating OperatingCurrent
Vcc = MAX, Outputs open
RE = WE = Vil,f=MAX
Com
150
140
130
120
mA
Mil
ICC2
Standby Current
RE = WE = RS = Vih
Com
15
15
10
10
Mil
QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
For 15 ns Commercial, 20, 25, 35, 50 ns Commercial/ Military, 120 ns Military
COMMERCIAL VCC=5V+10%, TA=0°C to +70°C, MILITARY VCC=5V±10%, TA=-55°C to +125°C
Symbol
Parameter (1)
Note
-40
-33
-25
-20
Unit
Type
f RC.fWC
Read or Write Clock, mHz
40
33
25
2
20
mHz
Min
tRC.tWC
Read or Write Cycle Time
50
25
30
40
ns
tew
Read or Write Clock High or Low
1
10
12
15
20
ts
Enable, Write Data Setup Time
5
6
7
8
tH
Enable, Write Data Hold Time
0
0
0
0
tCF
Clock to Flag Output Delay
8
10
12
15
Max
tCD
Clock to Data Output Delay
7
8
9
10
tRS
Reset Pulse Width
1
15
20
25
35
Min
t RSR
Reset Recovery Time
3
10
10
10
10
t RF
Reset to Flag Delay
12
15
17
20
Max
t EFL, t FFL
Flag Latency, R/W to E/F
4
12
15
17
20
Notes: These timings are measured as defined in AC Test Conditions
1 . Pulse widths less than the specified minimum value may upset the internal pointers and are not allowed.
2. These values are guaranteed by design and not tested
3. Minimum time to write clock edge for valid write enable to be accepted.
4. Time required from write clock edge to read clock edge for write to turn off empty on next clock;
Time required from read clock edge to write clock edge for read to turn off full on next clock.
AC TEST CONDITIONS
+5V
1.1KQ
To Output Pin q
680 n
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3 ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
30 pF* * Includes jig and scope
capacitances
3-58
QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
TIMING
tew
tRC
-
*i
tew
Valid Data
tCF
^ Valid Flags
and Write Operations
-
EFR
HFR.FFR
Reset Timing
QUALITY SEMICONDUCTOR INC.
3-59
QS7223, QS7224
=====
OPERATIONAL DESCRIPTION
The 7223/4 Clocked FIFO consists of a dual port RAM, read and write address counters, a flag comparator,
and synchronizing flip flops for the flags. A simplified block diagram of the 7223/4 Clocked FIFO is shown
below. Note that the internal design of the 7223/4 Clocked FIFO is more complex than shown for
maximum performance. The simplified block diagram shown is provided for understanding the operation
of the FIFO. For detailed timing in formation, refer to the AC Specifications and timing diagrams.
fr. DATA OUT
Q0-Q8
Clocked FIFO Simplified Block Diagram
The dual port RAM is a static RAM with two independent sets of addressing logic. Each set of addressing
logic can simultaneously and independently address words in the RAM. Each combination of addressing
logic and its associated data I/O is called a port, hence the name dual port RAM. In the FIFO, one port is
used only for writing and one port only for reading. If both ports have the same address and data is written
by one port, the same data will be read immediately by the other port. The data is said to flow through the
RAM.
The read and write address counters address the read and write ports of the dual port RAM. Each is a
binary counter that increments on the rising edge of the clock, is enabled for counting by a low active
enable signal and is asynchronously reset by a reset pulse. They are similar in operation to the 74161
binary counter.
Data is written into the dual port RAM by each write clock. Data is rewritten by each clock until a write enable
advances the write address counter. When the write address counter advances, the data written by the
last write clock, the one that advances the counter, is the data retained by that RAM word. Data is read
continuously by the read port at the address from the read address counter. If the FIFO is empty, data from
the write port will flow through to the read port following each write clock pulse. When read enable is
active, the read address counter advances to the next word.
The flag comparator continuously compares the contents of the two address counters. If the contents of
the two address counters are equal, the FIFO is empty, and the empty flag is active. This is the case
immediately after a reset pulse when both counters have been reset to zero. If the write address counter
value is equal to the read address counter value plus the depth of the RAM (e.g., 4096 for a 4Kx9 FIFO),
the FIFO is full, and the full flag is active. The counters are one bit longer than the address required for the
dual port RAM in order to make this comparison. This extra, most significant bit is used only by the flag
comparator If the write address counter value is larger than the read address counter value plus half the
QS7223, QS7224
depth of the RAM plus 1 (e.g., 2049 for a 4Kx9 FIFO), the FIFO is more than half full, and the half full flag is
active. The flag outputs from the flag comparator are synchronized in flip flops by the appropriate read or
write clocks so they change only following the rising edge of a clock.
Read and write enable are inhibited by the empty and full flags, respectively. If the FIFO is empty, read
enable is inhibited because there is no next word in the FIFO to step to. If the FIFO is full, both the write
enable and the write clock to the dual port RAM are inhibited because there is no place available to write
another word. (The gates corresponding to these read and write enable inhibits are not shown on the
simplified block diagram.) Note that when there is one word in the FIFO, read enable is allowed because
the FIFO is stepping to the empty state to await another word. Write enable and read enable can be
considered as "write next word" and "read next word," respectively.
The general operation of the 7223/4\Clocked FIFO is shown in the following timing diagrams.
wc
- 1
WE
1 i
r
FFR
rite Data
Not Full
Full
»
•
wrlte FIFQ tQ Fu"
RC [
*E |
EFR
» —
Not Empty
Read Data
Empty
Read FIFQ to Empty
QUALITY SEMICONDUCTOR INC.
3-61
QS7223, QS7224
WE
Write Data
DO 8
t__i — i r
1234
1 I
—I
^ t EFL — ■*
RC
RE~
efr"
— LJ-
I I
I
[
L
Empty
' \ '
*
1234
Write. Read One Word to Empty FIFO
«n i l
WE
rn r
Write Data mm
FFR
RC
RE
Full
t FFL
I Valid
Not Full
Full
Read Data
7654 |
1234
Read. Write One Word from Full FIFO
3-62
QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
APPLICATION INFORMATION
Width Expansion
The 7223/4 Clocked FIFOs may be expanded in width by connecting the read and write clocks and
enables and the reset lines of the FIFOs in parallel. The flags on all FIFOs will track, so any FIFO can be
used for flag information.
Bus Width Funneling
The 7223/4 FIFOs simplify bus width tunneling in high speed systems. Bus width tunneling is where data
must pass between two buses of different width, such as 32 bits and 8 bits. Funneling with the 7223/4
FIFOs is accomplished with external logic. The advantage of the 7223/4 Clocked FIFO interface is the
simplification of the timing parameters for the funneling action. Funneling logic requires deciding which
FIFOs are to be enabled for read or write on a particular cycle. For example, on a 32-bit to 8-bit transfer, 32-
bit data is written into four FIFOs simultaneously. The 8-bit data is read out of the four FIFOs in round-robin
fashion. With the 7223/4, most of the clock cycle is available for the round robin FIFO enable decision,
since
Depth Expansion
The 7223/4 is designed to be easily expanded in depth without additional logic by interconnecting the
flags and enables of the FIFOs. The 7223/4 have empty and full flags which are compatible with their write
and read enables, respectively. A depth expansion example is shown below. In this example, the flags
and enables are interconnected, and the write clock is used to transfer data between the FIFOs. In
general, the faster of the free running read or write clocks is used to clock data between the FIFOs.
Write Data 1
HEPJ
WD1
RD1
FFR1
WET
EFR1
RET
R~5
>WC
RC^
FIFO 2
Cascading Two 7224 FIFOs to Make an 8Kx9 FIFO
When the FIFOs are cascaded, data will be clocked from one FIFO to the next until an empty or full flag
inhibits transfer by disabling the write or read enable of the other FIFO respectively as will as disabling the
internal read or write, respectively, of the FIFO with the empty or full condition. This provides automatic,
orderly transfer between the FIFO with a fall through time of the order of two clock times per FIFO in
cascade. Timing diagrams for cascaded FIFOs are shown below.
=
QUALITY SEMICONDUCTOR INC.
3-63
QS7223, QS7224
wc
RC
WET
Write Data 1
Read Data 1
Write Data
I
— I
1
I
1
■ 1
*
i
I
{
I
*
i
j
1
i
I 1
P
m^mm ; i g ^ n i n ws;mm
(Never Full)
Not Empty
i
1
Empty
" j
i
i
4
EFR2 Empty
Read Data 2
1111
One Word Fall Through Two Empty FIFOs In Cascade
WC.RC
WET
Write Data
1
i r i r i
uj u uj m
mi
FFR2->RE1 (Never Full)
EFR1->WE2 Empty
Read Data 1
Write Data 2
2222
3333
4444
5555
Not Empty
1111
2222
3333
EFR2 Empty
Read Data 2
Not Empty
1111
Multiple Word Fall Through Two Empty FIFOs In Cascade
3-64
QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
=====
RC
RES
Read Data 2
EFR1->WE2
Read Datal
Write Data 2
FFR1
! I —
i n
1 — 1 1 —
I L
J |
«
!
7654
5432
:
s
s
1 ' i
Full
| Not Empty ■
■ Continuous En
Not Full
Full
j
4 !
i
#
able
j
Data Waiting to be Written = 1234
Next Word = 4567
! j
Not Full
Full
we
RC
RE2
Read Data 2
FFR2->RiT
EFR1->WE2
Read Datal
=WriteData2
FFR1
I
1
1
J L
8888
7777
6666
5555
4444
Not Full
Full
Not Empty i
■ Continuous En
able
Latched Data Waiting to be Written = 1234
3456
4567
i j
Not Full
Full !
Multiple Word Fall Through Two Full FIFOs In Cascade
=====
QUALITY SEMICONDUCTOR INC.
QS7223, QS7224
WC
RC
wet"
Write Data 1
EFR1->WE2
Read Data 1
Write Data 2
1
1111
FFR2->RE1
Empty
1 — I L
Tf
EFR2 Never Empt)|
! Not Empty
1111
!
!
re2 s — — \_j ! r
Read Data 2|
7654
5432
Detail of InterFIFO Transfer Handshake
One Wprd Transfer, First FIFQ Initially Empty, Second FIFO Initially Fgll
-
3-66
— — — — — — — ^— ^—
QUALITY SEMICONDUCTOR INC.
s
QS7306
Q
64K x 4 Ultra Deep
FIFO Memory
QS7306
ADVANCE
INFORMATION
64Kx4 Ultra Deep FIFO
Reversible ( A to B or B to A)
OE control pin
1/2, 1/4, 1/16, 1/32 status flags
Directly cascades with another UD FIFO
DESCRIPTION
50 MHz clocked interface
Simultaneous read arid write
Empty and Full fl
24-pin DIP
=
The 7306 is a high density, high performance , 64K deep, 4-bit-wide FIFO. The 7306 has clocked
interface with a single clock common to both its ports. Clock enables allow independent data transfer on
either port at rates to 50 MHz, up to and including simultaneous read and write on both ports at 50 MHz.
It is capable of moving data from port A to port B or from port B to port A. The direction is set upon reset
by the direction control pin. The 7306 allows simultaneous read and write operations at speeds up to
50MHz. All operations occur on rising edge of the clock. The 7306 has an output enable pin which
controls the port that is configured for read operation. The 7306 directly cascades to another 7306 or to
QSI's 8224 clocked FIFO with no external logic. The 7306 has an Empty flag, a Full flag and 1/2, 1/4,
1/8, 1/16, and 1/32 status flags.
=
FUNCTIONAL BLOCK DIAGRAM
Port A ^-t»r
AO -A3
DIR
ER£,~EN~B
CLK
WS
OE
H DirFF
gist
X
a>
"3
A
Q.
CO
O
PortB
B0-B3
Read Counter
Write Counter
Flag Counter
FF.EF
F2K...F32K
QUALITY SEMICONDUCTOR INC.
=
QS7306
PIN CONFIGURATIONS
■
■
3-68
QUALITY SEMICONDUCTOR INC.
Q
QS7316
64K x 4 Ultra Deep Qstjib
Burst Mode Dual Port RAM info^a™n
FEATURES/BENEFITS
• 64Kx4 Ultra Deep Dual Port • Single 50MHz clocked interface
• Allows simultaneous access on both ports • Simultaneous burst access on both ports
• 4 cycles first read access, 1 cycle burst read access • 32-pin package
• All operations occur on rising edge of clock • 64Kx4 internal single-port RAM architecture
• 2 cycle first write access,1 cycle burst write access
DESCRIPTION
The 731 6 is a high density, high performance , 64K deep, 4-bits-wide dual port SRAM with burst mode.
The 7316 has clocked interface with a single clock common to both its ports. Each port can be read from
or written to in a random access manner as well as in the burst mode. The 731 6 allows simultaneous read
and write operations at speeds up to 50MHz. All operation occur on rising edge of the clock.
The 731 6 may be addressed randomly or sequentially (burst) on either port. Address counter registers
provide the addresses for sequential access and built-in control logic allows simultaneous access on both
ports with the provision of three clocks (max) for first access and one clock burst access thereafter.
Two function control bits are used to control each port interface. The select the functions of Load Address
for Read (LAR), Load Address for Write (LAW), Next Word (NW) for burst transfers, and HOLD. The Load
Address functions cause the address register to be loaded on the rising edge of the clock. The 7316 uses
a multiplexed address bus for each of its ports. When an LAR or LAW code is presented, the 8 most
significant bits (MSBs) on the address bus are loaded into an address latch. On the rising edge of clock,
the 16-bit address counter is loaded with the 8 MSBs from the address latch and the 8 LSBs from the bus.
FUNCTIONAL
Port A
DA0-DA3
BLOCK DIAGRAM
xni
istei
a
X
c
iL
t Reg
32Kx8
SRAM
O)
a
OC
^5
A
Inpu
'Utpi
CO
i i
O
ADDAO-7
R5
AFC0.1
CLK
3_
Latch
A Counter
Latch
IT
B Counter
a
r
PortB
DB0-DB3
ADDBO-7
BFC0.1
—
QUALITY SEMICONDUCTOR INC. 3-69
QS7316
PIN CONFIGURATIONS
32 □ VCC
31 □ADDB7
30 "3 ADDB6
29 IIADDB5
28 □ADDB4
27 □ADDB3
26 □ADDB2
25 □ADDB1
24 □addbo
23 □ BFCO
22 □ BFC1
21 □ RS
□ 13 20 □ DB
C 14 19 □ DB
C 15 18 □ DB
Qj6 17p DB
i
;
" -
1
1
-
t+4
T
3-70
QUALITY SEMICONDUCTOR INC.
General Information 1
Static RAM Products 2
FIFO Memory Products 3
QuickSwitch Products 5
Application Notes 6
Quality And Reliability 7
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
-
QUALITY SEMICONDUCTOR INC.
FCT-T Table of Contents
—
FCT-T LOGIC PRODUCT DATA SHEETS
FCT-T Ordering Information
FCT-T Test Configuration
29FCT52/3
29FCT520/1
54/74FCT1 38/238
54/74FCT1 39/239
QS54/74FCT1 51/251
QS54/74FCT1 53/253
QS54/74FCT15725
QS54/74FCT161/3
QS54/74FCT191
QS54/74FCT193
QS54/74FCT240/1/4
QS54/74FCT245/640
QS54/74FCT273
QS54/74FCT280/1280
QS54/74FCT299
QS54/74FCT373
QS54/74FCT374
QS54/74FCT377
Registered Transceivers
Pipeline Registers
3- >8 Binary Decoders
Dual 2->4 Binary Decoders
8 Input Multiplexers
Dual 4 Input Multiplexers
Quad 2 Input Multiplexers
4- bit Binary Synchronous Counters
4-bit Binary Up/Down Counters
4-bit Binary Up/Down Counters
8-bit Buffers
8-bit Transceivers
8- bit Register with Clear
9- bit Parity Generator/Checkers
8-bit Universal Shift Register
8-bit Latch
8-bit Register
8-bit Register with Clock Enable
QS54/74FCT521 8-bit Identity Comparator
QS54/74FCT540/1
QS54/74FCT543/4
QS54/74FCT573
QS54/74FCT574
QS54/74FCT646/8
QS54/74FCT651/2
QS54/74FCT821/3/5
QS54/74FCT827/8
QS54/74FCT833/53
QS54/74FCT841/3/5
8-bit Buffers
8-bit Latch Transceiver
8-bit Latch
8-bit Register
8-bit Registered Transceiver
8-bit Registered Transceiver
8, 9 and 10-bit Registers
10-bit Buffers
Transceivers with Parity
8, 9 and 10-bit Latches
4-3
4-4
4-27
4-35
-43
-49
-55
-61
-67
-73
4-81
4-89
QS54/74FCT861 /2/3/4 9 and 1 0-bit Transceivers
4-97
4-103
4-109
4-115
4-123
4-129
4-135
4-141
4-147
4-153
4-159
4-167
4-173
4-179
4-187
4-195
4-205
4-211
4-213
4-223
QUALITY SEMICONDUCTOR INC.
4-1
FCT-T Table of Contents
FCT2000-T SERIES RESISTOR LOGIC PRODUCT DATA SHEETS
■
29FCT2052/3
29FCT2520/1
QS54/74FCT2151/251
QS54/74FCT2 153/253
QS54/74FCT2 15725
QS54/74FCT2161/3
QS54/74FCT2191
QS54/74FCT2193
QS54/74FCT2240/1/4
QS54/74FCT2245/640
QS54/74FCT2273
QS54/74FCT2280/1 280
QS54/74FCT2299
QS54/74FCT2373
QS54/74FCT22374
QS54/74FCT377
QS54/74FCT2521
QS54/74FCT2540/1
QS54/74FCT2543/4
QS54/74FCT2573
QS54/74FCT2574
QS54/74FCT2646/8
QS54/74FCT2651/2
QS54/74FCT2821/3/5
QS54/74FCT2827/8
QS54/74FCT2833/53
QS54/74FCT2841/3/5
QS54/74FCT2861/2/3/4
•
Registered Transceivers
Pipeline Registers
8 Input Multiplexers
Dual 4 Input Multiplexers
Quad 2 Input Multiplexers
4-bit Binary Synchronous Counters
4-bit Binary Up/Down Counters
4-bit Binary Up/Down Counters
8-bit Buffers
8-bit Transceivers
8- bit Register with Clear
9- bit Parity Generator/Checkers
8-bit Universal Shift Register
8-bit Latch
8-bit Register
8-bit Register with Clock Enable
8-bit Identity Comparator
■
8-bit Buffers
8-bit Latch Transceiver
8-bit Latch
8-bit Register
8-bit Registered Transceiver
8-bit Registered Transceiver
8, 9 and 1 0-bit Registers
10-bit Buffers
Transceivers with Parity
8, 9 and 10-bit Latches
9 and 10-bit Transceivers
M3C
4-27
4-35
4-55
4-61
4-67
4-73
4-81
4-89
4-97
4-103
4-109
4-115
4-123
4-129
4-135
4-141
4-147
4-153
4-159
4-167
4-173
4-179
4-187
4-195
4-205
4-211
4-213
4-223
4-2
QUALITY SEMICONDUCTOR INC.
FCT-T Ordering Information
QSXXFCT XXX X I XX X
QS29FCT XXX X I XX X
Processing
\ Package type
. FCT-T
Designation
1 Speed grade
1 Device type
1 54 Military
I 74 Commercial
Processing
i Package type
_| FCT-T
Designation
H Speed grade
H Device type
[Designation
Family
Speed Grades:
Blank - Standard
A
B
C
D
Processing:
Blank - Standard
B - MIL-STD 883
Package Type:
P - Plastic DIP, 300 mil
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
=
QUALITY SEMICONDUCTOR INC.
4-3
—
FCT-T Test Configuration
—
Vcc
Vi
Pulse
Generator
DUT
50 Q
50 pF
500 a
-cT^o-o 7.ov
Parameter
Tested
Switch
Position
t PLZ, t PZL
Closed
All Others
Open
50Q Coax to
Oscilloscope
Note: For detailed testing conditions and circuitry see FCT-T family characteristics
■
■
iC
4-4
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
FCT-T Family Circuit Characteristics
FCT-T Logic Family Characteristics
FCT Logic was introduced in 1 985 as a low power CMOS replacement for the popular 74F series bipolar
logic. It became popular almost immediately, and it is now a JEDEC standard logic family available from
multiple vendors. Specifications on the original FCT logic family were, by intent, exactly the same as their
74F bipolar equivalents except for significantly lower power: FCT devices typically required less than 50
mW versus 500 mW or more for 74F, a 90% power savings.
While the original FCT logic family has its outputs typically swing from ground to 4.5V, the state-of-the-art
FCT logic family have reduce output voltage swings, from ground to typically 3.5V. This makes the family
more compatible with TTL logic and help to control system noise at high speeds. The reduced output
swing FCT logic is denoted FCT-T, and all its part numbers carry a suffix T after the speed grade letter. In
this chapter we use FCT and FCT-T interchangeably. All QSI FCT products have reduced output swing
and are marked 74QSFCTXXXYT (e.g. 74QSFCT138AT).
When the FCT-T family was introduced, testing showed that the parts were significantly faster than the
bipolar parts they replaced. The advantage of using advanced CMOS technology resulted in an immediate
25 to 35% speed improvement. These higher speed parts were identified by an "A" suffix. This
immediately made them the fastest TTL logic available. FCT-T continues to be the fastest TTL logic family,
as successive improvements have resulted in additional speed grades including "B", "C" and now "D"
grades, with each speed grade being 20-35% faster than the previous grade. The continual improvement
in FCT-T performance follows the general trend of performance improvement of CMOS technology. This
allows FCT-T to keep pace with the continual performance improvement of other system components.
The FCT-T family from QSI has additional features and options available to the system designer. FCT-T
from QSI has hysteresis on all inputs, which reduces noise sensitivity for signals with slow rise and fall
times. QSI has also introduced the FCT2000 series resistor family which adds an on chip 25fl resistor to
each output. This resistor significantly reduces system noise and ringing without reducing speed. Adding
series resistors has been a common design practice in high speed systems for many years. QSI supports
this practice by providing the resistor inside the part. This reduces the board space required and allows
the speed of the part to be specified with the resistor included. QSI was the first to extend this concept to
the full FCT-T family and to fully specify and control the resistor value. For each standard FCT-T part (e.g.
FCT244), QSI also offers a resistor output version (e.g. FCT2244).
QSI has also pioneered new packages for logic to reduce board space and increase performance. The ZIP
package provides a 50% space savings over a PDIP, providing surface mount density in a through-hole
environment. The Quarter-size Small Outline Package (QSOP) is half the length and half the width of the
SOIC it replaces, resulting in a four times increase in board density.
High Performance CMOS Technology
High performance CMOS technology has revolutionized logic. In 1980, bipolar was the logic of choice for
high speed systems. CMOS, although very low power, was ten times slower and used only where its low
power was a significant advantage. That all changed with the development of high performance, short
channel length CMOS technology and the corresponding creation of the FCT family. Suddenly, CMOS
was the fastest technology, and bipolar was the medium speed, power hungry prior logic generation. This
happened because of differences in the potential for improvement of each technology.
Improvement in semiconductor technology is driven by improvement in the precision of creating patterns
on the silicon - called lithography, as governed by the optics of the machines which project these patterns.
This precision is specified by the smallest feature that can be reliably printed, the minimum feature size.
=
QUALITY SEMICONDUCTOR INC. 4-5
FCT-T Family Characteristics
Processes are identified by this feature size, e.g. 1 .0 micron CMOS. Increased precision allows the
creation of smaller devices. Smaller devices are faster devices; however, there is a difference between
CMOS and bipolar types. CMOS improves much more rapidly than bipolar with reduction in device size.
In a bipolar device, the delay of a gate is determined by the capacitance of the device divided by the
current through the device. To improve the speed, one should increase the current and decrease the
capacitance. Increasing the current is not practical: it is already set at the highest value the power
dissipation the package will allow, usually 1 00 to 1 50 mA for PDIP packages. This is the source of the well
known speed-power product (actually a speed-current product) of bipolar logic. The only other possibility
for increasing the speed is to decrease the capacitance by decreasing the device size. This too has a limit.
The device must be a certain minimum size to support the current available to it. This minimum size defines
the minimum capacitance, and therefore the speed-power product limit. Reducing the device further will
reduce the capacitance, but the current must be reduced as well. As a result, bipolar devices have
improved only slowly over time, from the 20+ ns delay of the 7400 in 1965 to the 5 ns delay of the 74F00
of today.
In a CMOS device, the delay of a gate is determined by the product of the channel on resistance and the
gate capacitance. Decreasing the feature size to make the CMOS devices smaller reduces both the on
resistance and the gate capacitance, resulting in a delay improvement at roughly the square of the rate of
improvement in feature size. For example, a 1 0% reduction in feature size provides a 1 0% reduction in
gate length. This causes at least a 10% reduction in on resistance and a 10% reduction in gate
capacitance. As a result, a 10% reduction in feature size provides a 20% reduction in gate delay. The
performance improvement in going from 3 micron CMOS to 1 micron CMOS should be of the order of a
factor of 1 0. This is the source of the dramatic transition of CMOS from 50 ns gates in 1 975 to a 4 ns gates
in 1985.
CMOS is also the technology of the future. Unlike bipolar and GaAs devices, CMOS is not speed-power
limited. The CMOS device is voltage driven. It only draws power when it switches. Bipolar and GaAs
devices are current amplifiers, however. They must draw current when they are on in order to stay on.
Bipolar and GaAs devices are capable of very high speeds when unlimited power is available, such as in
single transistors and small logic devices. However as the chip size increases, package power dissipation
limits convert the speed-power product into a speed-density product. The bigger you make it, the slower it
gets because each gate you ad must draw power even if it is not switching.
CMOS does not have the bipolar speed-power problem. Gates which are not switching draw no power.
This is a significant advantage in LSI designs. Very often, a large portion of the system logic is used
infrequently or switches at a low frequency. This logic can be combined into one chip with little increase in
the chip power. This allows increasing integration without speed degradation.
CMOS does have a speed-power effect, however. Each gate draws a small amount of power when it
switches, resulting in a power dissipation component that increases with frequency. This is equivalent to
the power required to charge and discharge an effective internal capacitance. For FCT logic, this effective
internal capacitance is roughly equal to the typical load capacitance seen by the device. Also, this effective
internal capacitance decreases with each improvement in speed of the device.
QCMOS™ Technology
QCMOS™ is representative of the current state-of-the-art in high speed CMOS technology. QCMOS™ is
currently being produced in 1 .0 micron and 0.8 micron versions with a development path to 0.5 micron
and below. It is a dual-well, ion-implanted technology with substrate bias to reduce body effect
capacitance and prevent latchup. QCMOS™ uses shallow, ion implanted junctions for low capacitance and
high speed for a given device size. QCMOS™ technology also provides lower on resistance for a given
device size. The result is very high speed for a given feature size, providing almost a full generation of
speed improvement.
QCMOS™ has the additional advantage that it is relatively insensitive to temperature. QCMOS™ device
characteristics typically vary only 1 0% over the full temperature range, as compared to 30% for other high
4-6
QUALITY SEMICONDUCTOR INC
FCT-T Family Characteristics
performance CMOS technologies. An example of the temperature characteristics of QCMOS™ is shown
below in the plot of propagation delay versus temperature for the FCT373. The stable temperature
characteristics of QCMOS™, coupled with 6 transistor SRAM cell technology allows manufacture of high
performance devices for wide temperature range applications such as military and space equipment.
10%
8%
6%
2 4%
2%
0%
-2%
-4%
• -6%
-8%
3
■
>
(0
-75
Change In Delay vs Temperature for FCT373
■ 50
■25
25
iO
-1-
100 125
FCT373
■
I
QUALITY SEMICONDUCTOR INC.
4-7
i
FCT-T Family Characteristics
FCT-T Circuitry
FCT-T logic consists of standard input and output circuits combined with specific logic for each member of
the family. The FCT244 logic bbck diagram shown below is an example of a typical FCT-T design. The
FCT244 is a simple buffer, consisting of input buffers, output drivers, and output enable logic.
244 Logic
Pull Up
Data In [ ^-j-C
[
0"E
Data Out
. * * t
FCT244 Logic Block Diagram
■
Input Characteristics
The input characteristics of the FCT-T family are determined by the input buffers. A circuit diagram of an
input buffer is shown below. It consists of an inverter, an input undershoot clamp and a hysteresis circuit.
Hysteresis
"Vcc
Input Clamp
Inverter
'"vcc"
TTL In
MP2
-►To FCT
Circuit
FCT-T Input Buffer Circuit Diagram
The inverter is designed to provide an input threshold of approximately 1 .40 volts for TTL compatibility.
This is accomplished by adjusting the sizes of the two transistors, MP1 and MN1 . This is affected by the
hysteresis circuit consisting of MP2 and X1 . When the input is high and going low, the inverter output is
low and the hysteresis transistor, MN2, is off and the high-to-low threshold is approximately 1 .4 volts.
When the input is low and going high, the inverter output is high and MP2 is on. MP2 increases the
threshold by approximately 0.2 volts so that the low to high threshold is approximately 1 .60 volts. This 200
millivolts of hysteresis reduces noise sensitivity for signals passing through the threshold region.
4-8
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
The input buffer circuitry does not draw current when the input is at 0.0 volts or at Vcc. When the input is at
0.0 volts, MN1 is off and no current can flow from either MP1 or MP2. If the input is at Vcc, both MP1 and
and MP2 are both off, and no current flows. When the input is between 0.0 volts and Vcc, both MN1 and
MP1 are partially on, and current flows between Vcc and ground. This is the source of the by Alec
specification which defines the maximum current drawn by an input buffer when the input is at the typical
The transition point indicated by the current peak is approximately 1 .6 volts. A similar plot for a low to high
transition would show a transition point of approximately 1 .4 volts. Note the step in the current provided by
the hysteresis circuit.
4.50
4.00
3.50
3.00
<
E
2.50
t
2.00
1.50
1.00
0.50
0.00
■
1 1 ■! ■—
0.00
0.
1.00
1.50
2.1
2.50
3.00
Input Voltage, Volts
versus Input Voltage for
to Low Transition
■
QUALITY SEMICONDUCTOR INC.
4-9
FCT-T Family Characteristics
Input Clamp
The input clamp, MN2, turns on when the input goes negative, providing clamp action for negative
undershoot transients and thereby reducing system noise. Note that there is no positive clamp. The input
can go above Voc without conducting current. In fact, actual input leakage is of the order of a few
nanoamperes over the input range of 0.0 to 5.0 volts at room temperature. A graph of typical input
characteristics is shown below.
0
-50
•100
-150
•200
•250
•300
■
•350
•
-2.5
-1.5
-1.0
Input Voltage, Volts
-0.5
0.0
2.0
1.0
2.0 3.0
Input Voltage, Volts
FCT-T Input Characteristics
4.0
5.0
4-10
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
Output Characteristics
The output characteristics of FCT-T logic are determined by the output buffer circuit. A schematic of an
FCT-T buffer is shown below. There are two types of output circuits, one rated at 48 mA and one rated at
64 mA. These ratings correspond to the ratings of 74F circuits from which the FCT-T family was derived.
Pull Up Circuit
~Vcc"
FCT-T Output Buffer Circuit Diagram
The output circuit consists of two parts, a pull up circuit and a pull down circuit. The pull up circuit
determines the Voh characteristics and the pull down determines the Vol characteristics. The pull up
circuit consists of a single transistor, MN3. This transistor pulls the output up to approximately 4.0 volts
under no load and 3.5 volts under light loading. This results in the Voh/loh characteristics shown below.
Note that since the pull up device is an N channel transistor, the output may be taken above Vcc without
clamp action. This means that when Vcc is removed from the FCT-T device, it will not draw current above
leakage amounts on its outputs. This allows QSI FCT-T devices to be powered down without loading a bus
to which it may be connected.
■
QUALITY SEMICONDUCTOR INC.
4-11
0.00
•40.00
| -60.00
o -80.00
•100.00
-120.00
-140.00
0.0
1.0
■
^lope = 2512
— —
\r~ —
2.0 3.0
Voh, Volts
4.0
5.0
FCT-T Voh ys loh Characteristics
The Vol characteristics are determined by the pull down circuit. The DC Vol versus lol characteristics are
determined primarily by the large driver transistor, MN2. A plot of lol versus Vol for an FCT373 device with
48 mA current rating is shown below.
100.0
80.0
< 60.0
E
£ 40.0
20.0
0.0
0.2 0.3
Vol, Volts
0.4
0.5
FCT-T Vol vs lol Characteristics for FCT373. 48 mA Drive
4-12
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
The Vol characteristics shown above are for standard output FCT-T devices. A 25ft resistor output option
is available for all QSI FCT-T devices for system noise suppression. This option adds resistors R2 and R3,
shown above in the output buffer schematic. These resistors are both shorted to zero ohms in the
standard version. In the 25Q version, resistor R2 is 25Q, while resistor R3 remains at zero ohms. This
results in a 28-30 ohm nominal output resistance when the output is low, consisting of 25 ohms for the
resistor and 3-5 ohms typical for the output transistor, MN2. The resistor R3 is kept at zero ohms because
the effective output resistance of the pull up transistor, MN3, is approximately 25 ohms in the region
around the TTL threshold of 1 .5 volts.
The output pull down circuit consists of two parts: an initial pull down transistor, MN1 , and the main pull
down transistor, MN2. This provides a two-step pull down characteristic. MN1 is turned on initially and
provides a moderate pull down drive. At a later time determined by the combination of R1 and capacitor
C1 , the main drive transistor MN2 is turned on. The turn on time of MN2 can be adjusted by changing the
value of resistor R1 . This two stage turn on circuitry provides control of the output high to low transition in
order to control ground bounce noise. (See Application Note AN01) Resistor R1 is adjusted to provide
the best tradeoff of speed versus ground bounce noise.
When the output buffer is shut off, both the pull up and pull down transistors are shut off. The outputs
may be taken above Vcc without current flow beyond a few nanoamperes of leakage. Taking an output
below ground, however, will result in clamping action from the pull down transistors, MN1 and MN2, with
clamp voltage and current characteristics similar to the input clamp characteristics discussed above.
Parameter Variations with Load
FCT-T propagation delay is affected by capacitive load, increasing with added load as shown below.
QUALITY SEMICONDUCTOR INC.
4-13
FCT-T Family Characteristics
Unit Loading ft Fanout
In system designs, TTL devices drive other TTL devices. There are practical limitations on how many
devices a given TTL device - such as an FCT-T device - can drive. This is defined as fanout, the number of
other devices a given device can drive. Because of the high drive capability of FCT-T (48 or 64 mA
minimum) and the low input current requirements of FCT-T (5 uA, maximum) and other popular logic
families, DC fanout of FCT-T is quite large, from 1 00 to 1 000+ depending on the TTL devices being
driven.
The fanout of a high performance logic family such as FCT-T determined by AC, not DC requirements.
There is an effective AC fanout limit determined by the speed/fanout tradeoffs of a given design. FCT-T
device AC performance is specified with a 50 pF load. For an input capacitance of 5-7 pF, this corresponds
to an AC fanout of 7-1 0 if the data sheet specification is to be met. Loads above 50 pF will incur a
propagation delay penalty of approximately 2.5 ns/100 pF of additional capacitance, as discussed in the
FCT-T Family Characteristics section.
High performance logic such as FCT-T has high DC drive capability to insure that it can drive high
capacitance loads. The DC drive capability of FCT-T is seldom used except for driving low impedance,
resistor terminated loads such as terminated cables or backplanes, the more typical case is driving high
capacitance, unterminated buses on PC cards or short backplanes. The high pull down drive specified by
lol and the high pull up drive specified by los insures that the FCT-T device can provide the current to drive
high capacitive loads. For example, a 100 pF load being driven at a fall time of 5 ns required a drive current
of (3.5/5)(10) = 70 mA. If high drive current capability were not provided, device performance would
degrade rapidly with capacitive loading because of the limit on capacitive charge/discharge current.
■
■
4-14
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
?uts Switchlri
Ground bounce noise is a noise coupling between outputs in high speed logic and Is function of package
and resistor option. This is discussed in detail in application notes AN01 , AN06, and AN07. Ground
bounce noise is a function of ground lead inductance, which is highest in the DIP package. The ZIP
package has a short ground lead, and the surface mount packages of SOIC and QSOP have shorter
ground leads because their overall size is smaller. FCT2000 series resistor option devices have lower
overall noise because of the damping action of the resistor; this reduces ground bounce as well. The chart
below shows typical relative ground bounce values for various packages for FCT devices from the same
wafer lot.
MULTIPLE OUTPUTS SWITCHING
BOUNCE
Ground
Relative
FCT2000 GB Relative
Package
Inductance G Bounce to Standard FCT-T
PDIP
ZIP
SOIC
QSOP
13.7 nH
5.3 nH
8.5 nH
3.6 nH
100%
62%
79%
51%
60%
60%
60%
60%
Parameter Variation with Multiple Outputs Switching: Propagation Delay
Propagation delay for TTL logic such as FCT-T is measured with one output switching. When multiple
outputs switch at the same time, there is an added propagation delay called package pushout. This added
delay is function of package and resistor option. Package pushout is related to ground bounce noise and
is a function of ground lead inductance, which is highest in the DIP package. The ZIP package has a short
ground lead, and the surface mount packages of SOIC and QSOP have shorter ground leads because
their overall size is smaller. FCT2000 series resistor option devices have lower overall noise and package
pushout because of the damping action of the resistor which reduces ground bounce. The chart below
shows estimated package pushout values for various packages for FCT devices from the same wafer lot.
MULTIPLE OUTPUTS SWITCHING ADDED DELAY
Package Added Delay
PDIP
ZIP
SOIC
QSOP
0.90ns
0.54ns
0.72ns
0.46 ns
QUALITY SEMICONDUCTOR INC.
4-15
rower mssipanun
The power requirements of FCT-T logic are much lower than the bipolar logic it replaces. Power
requirements for QSI FCT-T logic have four sources: quiescent current, input buffer current, internal
switching current, and load capacitance drive current. The quiescent current of QSI FCT-T is typically 0.5
mA which is primarily current for a substrate pump. This is specified as Ice on the QSI FCT-T data sheets.
The substrate pump provides bias for the substrate which reduces capacitance for increased speed.
TTL high of 3.4 volts. This is specified as Alec on the QSI FCT-T data sheets. For an octal device such as
an FCT244 with random data inputs of 50% duty cycle, this results in (8)(2.0)(50%) = 8 mA = 40 mW typical
power to the input buffers.
CMOS logic draws internal current when it switches. When the input of a CMOS gate - such as the inverter
in the TTL input buffer discussed earlier - transitions from low to high or high to low, there is a period of
time when both the N channel and P channel devices are both on. During this transition time, current flows
directly from Vcc to ground. This results in a certain amount of charge transferred equal to the average
current times the transition time. The charge transfer per switching event results in a frequency
dependent current, specified in mA per MHz as Qccd on the QSI FCT-T data sheets. This current
represents the aggregate charge transferred by all gates in an FCT-T device when it switches. Since
charge is transferred each time a gate switches, this is equivalent to charging and discharging a capacitor.
For a Qccd of 0.25 mA per MHz and a Vcc of 5.0 volts, this is equivalent to an internal capacitance of 50
There is an additional source of device current which is not specified on TTL data sheets but is an
important component of real system designs. This is the power required to charge and discharge external
bad capacitance. This current is a function of the Voh of the device, the load capacitance and the
frequency of the charge/discharge cycle. For QSI FCT-T logic with a typical Voh of 3.5 volts and a load
capacitance of 50 pF, this results in a current of 0.17 mA per MHz per output. For a data bus cycle time of
1 0 MHz (equivalent to 5 MHz square waves), an octal device such as an FCT244 would draw a load
capacitance charging current of (8)(5)(.17) = 7.0 mA.
=
4-16
QUALITY SEMICONDUCTOR INC.
=
FCT-T Family Characteristics
.
A combined plot of current versus frequency for FCT-T versus various other logic families is shown below
for a 244 device driving a bus with 50 pF load over a bus frequency range of zero to 30 MHz. Zero to 3.4
volt input swings are assumed so as to include Alec terms. Data for other logic families are taken from
published data.
110
Bus Frequency, MHz
Current Consumption for 244 Buffers from Various Logic Families
8 Inputs Switching between Q and 3.4 volts. 50 pF load
4-17
FCT-T Family Characteristics
Parameter Variations with Vcc
Propagation delay of FCT-T logic is slightly affected by changes in Vcc, as shown below. Increasing Vcc
causes internal increase in transistor gate voltage. This increases lowers on resistance, decreasing
internal RC time constants and total propagation delay.
Delay vs Vcc for FCT373
4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
VCC, Volts
Change In Propagation Delay versus Vcc for FCT373. Typical
■
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
Ratings, Specifications and Waveforms
■
General Comments
In this section, the ratings, specifications and waveforms used in the data sheets are discussed to provide
information on their meaning and how they are interpreted.
Absolute Maximum Ratings
The Absolute Maximum ratings define the limits of operation of the FCT-T devices. Operation beyond
these limits may cause permanent damage the device, i.e. it may no longer meet its specifications or may
even cease to function.
The Supply Voltage rating defines the absolute maximum Vcc voltage that can be safely be applied to tie
device. The Supply Voltage rating of FCT-T is consistent with the equivalent ratings of other TTL devices,
and system power distribution design must take these ratings into consideration for reliable operation.
The Supply Voltage rating is determined by the internal breakdown voltage ratings of the device. High
performance processes such as QCMOS™ strive to reduce device dimensions in order to increase
speed. Reducing device dimensions also tends to reduce breakdown voltages. If Vcc to the device is
taken too high, the internal device breakdown voltages may be exceeded, excessive current drawn, and
devices may be permanently damaged because of the high resulting power dissipation and heat
generated in the device. FCT-T devices typically have breakdown voltages well above the Supply Voltage
rating listed, care must be taken that the Vcc supply does not go above this rating, even transiently.
The Output Voltage rating defines the maximum voltage that can be applied to an output when it is in its
disabled state. Note that this voltage is independent of Vcc, and the output can go above Vcc. The device
can be powered down and not load its outputs. This is because there is no clamp diode to Vcc or P
channel pull up on the output.
The Input Voltage rating defines the maximum voltage that can be applied to an input. Note that this
voltage is independent of Vcc, and the input can go above Vcc. The device can be powered down and
not load its inputs. This is because there is no output clamp diode to Vcc.
The AC Input Voltage rating is an undershoot specification. Undershoot pulses of up to -3 volts can be
tolerated without damage to the device. However, large undershoot pulses can cause significant clamp
current and the energy of these pulses is dissipated in the device. If these pulses have a high duty cycle,
the average power and the average current in the undershoot pulses can be significant and must be taken
into account to insure that the DC Input Diode Current and the Maximum Power Dissipation ratings are not
exceeded.
The DC Input Diode Current defines the rating of the input undershoot clamp diode. The average current
from undershoot clamp pulses must be below this rating.
The DC Output Diode Current defines the rating of the output negative undershoot clamp diode. The
average current from undershoot clamp pulses must be below this rating.
The DC Output Current Maximum Sink Per Pin defines the maximum DC output current that can be drawn
per output to pull down an external load.
The Maximum Power Dissipation defines the maximum total power dissipation capability of the device. It
represents a package power dissipation limit for the device, above which the die will overheat and be
damaged. Note that the power dissipation limit includes power dissipated by the input clamp diodes as
well as power from Vcc for driving internal circuitry and external capacitive loads.
QUALITY SEMICONDUCTOR INC.
4-19
FCT-T Family Characteristics
^====^====s=s=======^=============
The Storage Temperature rating defines the maximum temperature that the packages may be subject to
for long term storage. Long term storage above this temperature may cause degradation of the chip. This
is a precautionary specification. Chips cannot be subjected to extremely high temperatures, significantly
above the Storage Temperature rating, even if unpowered and be expected to work reliably thereafter.
Input and Output Capacitance
Each input and output pin has a capacitance associated with it. This capacitance is a function of the
package and whether the pin in question is an input, output, or I/O pin. Pure input pins have the lowest
capacitance. Output pins have higher capacitance because of the capacitance contributed by the
relatively large output pull up and pull down transistors. Some devices, such as the FCT245, have pins
which are termed I/O, or input/output. These pins have the same capacitance as output pins because the
capacitance of the output driver transistors is present when these pins are in the input mode. Some
devices, such as the FCT244, have I/O capacitance on all pins even though it has many dedicated inputs.
This is because the FCT244 and FCT245 are derived from the same design, and the FCT244 inputs are
actually I/O pins even though the output drivers are never enabled on these pins.
DC Electrical Characteristics
The DC Electrical Specifications define the input requirements for valid operation, output specifications
during valid operation and responses to applied signals such as leakage currents, clamp voltages and
output resistance.
Vih defines the minimum DC input voltage for a TTL high. Typical TTL high voltages applied to inputs are
3.5 to 5.0 volts. ¥il defines the maximum DC input voltage for a TTL low. Typical TTL tow voltages applied
to inputs are 0.0 to 0.5 volts. Note that the AC characteristics are guaranteed for input switching values of
3.0 volts for a TTL high and 0.0 volts for a TTL low.
AVt defines the typical input hysteresis. This is the difference in input threshold voltages for low-to-high
and high-to-low input transitions. This specification guarantees that there is some hysteresis and gives its
typical value.
lit] and Jil define the maximum input leakage current; Jqz defines the maximum output off state leakage
current. The maximum input or output leakage is ±5 uA, and a typical value is 1 -5 nanoamperes at 25 °C.
los defines the minimum output short circuit current for an output being driven to a TTL high. This is the
minimum current sourced by the device when an output is grounded and insures that the device has
sufficient current to charge high capacitance toads in tow-to-high transitions.
Jots defines the minimum output short circuit current for a resistor output being driven to a TTL low. This is
the minimum pull down current by the device when an output is at 2.0 volts and insures that the device
has sufficient current to charge high capacitance loads in high-to-low transitions. It also intended to
indirectly guarantee that the output structure is a high current driver in series with a 25Q resistor, rather
than a weakened output which has a 25£2 resistance at low current but is unable to drive the currents
required for high capacitance loads.
YiC defines the input undershoot clamp voltage for a specified input current. It guarantees that the input
undershoot clamp is sufficiently low impedance to provide useful clamping action.
Voh defines the minimum output voltage for a TTL high. This is specified under two conditions: low
current and high current. The low current specification defines the typical TTL high output level for the
light loads seen in typical designs. The high current specification defines the minimum voltage under high
loading, and specifications are given for military and commercial conditions.
4-20
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
Vol defines the maximum output voltage for a TTL low. This is specified under two conditions: standard
and resistor output. The standard output specification is for conventional output, and specifications are
given for military and commercial conditions. It indicates the drive capability of the output. The resistor
output Vol specification is for 25Q resistor output devices under moderate DC loading.
Rout defines the range of resistance values for resistor output devices. It is guaranteed over voltage and
temperature. This is an incremental resistance measured at the test current. The resistance is calculated
as (Vout at 1 2 mA - Vout at 0 mA) divided by (1 2 mA - 0 mA).
I
6C0 Ope at
The DC Electrical Characteristics define the limits of operation for the device. The recommended
operating conditions are stated at the top of the DC Electrical Characteristics and Switching Characteristics
specifications. The recommended operating conditions are those the parts are expected to encounter in
normal operation. The switching characteristics are guaranteed under these conditions. The
recommended operating conditions conditions for FCT-T logic cover operating temperatures of 0 to 70 °C
for commercial and -55 to + 125 °C for military temperature range parts and a nominal Vcc voltage of 5.0
volts with an operating range of within +1 0% of this value (i.e. 4.5 to 5.5 volts).
Power Supply Characteristics
The Power Supply Characteristics defines the method for calculating the current drawn by the device from
Vcc during operation. This current has several components which combine to form the total current. The
Power Supply Characteristics specifies these components and how they combine to form the total.
There are four sources of power supply current, Ic, in FCT-T devices. They are: quiescent current, input
buffer current, internal switching current, and load capacitance drive current.
Ice is the quiescent current of QSI FCT-T and is the current drawn when the device is disabled and not
switching. It is the DC standby current.
Aj££ is the current the TTL input buffers draw when their inputs are between approximately 0.5 volts and
4.0 volts. The Alec specification defines the maximum amount of current drawn per buffer when the buffer
input is at a TTL high of 3.4 volts.
Qccd is the internal current CMOS logic draws when it switches. The charge transfer per switching event
results in a frequency dependent current, specified in mA per MHz.
Note that the Qccd term does not include any current required by switching an external capacitive load.
This current is a function of the Voh of the device, the load capacitance and the frequency of the
charge/discharge cycle. For QSI FCT-T logic with a typical Voh of 3.5 volts, this term is 0.35 mA per MHz
per 100 pF of load capacitance.
]£, the total current is the sum of these components. It is calculated as shown below.
QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
Power Supply Current Calculation
The following shows how to calculate the worst case power supply current, Ic, for typical operating
conditions.
-
lam Description
Ice
+ AlccxNxd
+ QccdxFx(M + 0.5xP)
+ 0.35xFxC/100xS
Where:
Quiescent current
Input Buffer current for inputs at 3.4 volts
Internal switching current, per MHz
External capacitive load current, per MHz, per pF
te = Total Vcc current
Ice = Quiescent Current
Alec = Input Buffer Current for Input at 3.4 Volts, per input
N = Number of Inputs @TTL High, 3.4 Volts
d = Duty cycle at TTL High
Qccd = Internal Switching Current, mA per MHz
F = Switching Frequency, MHz
M = Number of non-clock inputs switching
P = Number of clock inputs switching
C = Load Capacitance in Pf
S = Number of outputs switching while driving load capacitance, C
Example: FCT244, 8 inputs switching at 5 MHz (10 MHz bus data rate) @ 50% duty cycle,
8 enabled outputs, 50 pF loads
b
Tarn
Description
(1.5)
+ (2.5)(8)(0.5)
+ (0.25)(5)(8)
+ (0.35)(5)(50/100)(8)
1.5 + 10 + 10 + 7
28.5 mA Total Current
Quiescent current
Input Buffer current for inputs at 3.4 volts
Internal switching current, per MHz
External capacitive load current, per MHz, per pF
■
■
4-22
QUALITY SEMICONDUCTOR INC.
-
FCT-T Family Characteristics
Switching Characteristics
The Switching Characteristics, often called the AC Characteristics, define the propagation delay
characteristics of the device. There are usually several options, called speed grades, for each device.
These options are indicated by a suffix: "A", "B", "C", etc. The slowest speed grade may have no suffix
letter. These specifications correspond directly to the original 74F series specifications which FCT-T logic
was to meet. Higher letter suffixes refer to progressively faster speed grades, i.e. parts which have lower
propagation delay.
Propagation Delay Specifications: t PHL. t PLH
Propagation delay specifications such as t PHL and t PLH define the propagation delay from input to
output for flow through devices such as FCT244 buffers and FCT373 latches, and clock to output delay
for register devices such as FCT374. The maximum specifications indicate the maximum time delay
between application of the input or clock signal and the output switching to the correct level. Speed
grades are often determined by these specifications.
The minimum propagation delay times define a guaranteed time between change of the input or clock
signal and a corresponding change in the output signal. The designer can sometimes take advantage of
these minimum times to rely on the output being held for a time before change begins for the next cycle.
Minimum times are difficult to meet because they run counter to product improvement. A minimum delay in
effect states that the part will be no faster than this number. This wars against the continual effort to
improve the part by increasing speeds and reducing the maximum delays. Often, a production run will
produce parts faster than the required specifications. This is a benefit for guaranteed maximum
specifications; it could be a problem for guaranteed minimums. As a result, minimum specifications are
typically set by the fastest speed grade and applied to all slower speed grades.
Three State Propagation Delay Specifications: t PZH. t PZL. t PHZ. t PLZ
Three state specifications cover two conditions: going from the high impedance (high-Z) condition to the
low impedance, on state condition, and going from the low impedance, on state condition to the high
impedance (high-Z) condition. In the high-Z to low-Z case, propagation delay measurements are done in
the same manner as any other: the output must settle to the correct logic high or low state before the
stated maximum time, t PZH or LE2L.
In the low-Z to high-Z case, the output must be in the high-Z condition by the stated maximum time, t PHZ
or t PLZ. Special measurement must be done to detect the high-Z condition. Since the high-Z condition
means the output is not driven, the high-Z condition is detected by using an external resistor load network
to drive the output away from the previous high or low logic state to a level determined by the load
network. The output will start to move to this level when the output has turned off. This is detected by a
change in the output level away from the previous high or low. The output is defined as being in the high-
Z state when the output moves from its prior high or low state by 300 millivolts. This is shown in the
waveform diagrams below. Note that this specification is usually guaranteed by design, verified by device
characterization and not tested in production.
QUALITY SEMICONDUCTOR INC.
4-23
Voh
Out
Vol
EnaBFe
3.5-V
Voh
Vol
Waveforms for Measurement of t PLZ. t PHZ. t PZL. t PZH
■
Setup and Hold Time and ClocK Pulse Width Specifications; t S, t H, t W
Setup and hold times define a period during which a data or control input must be stable relative to a clock
edge such as the falling (high-to-low )edge of a latch enable signal for an FCT373 latch or the rising (low-
to-high) edge of a clock for an FCT374 register. Setup time, IS, is defined as stable time before the
clocking edge; hold time, Ltd, is defined as the stable time after the clocking edge. During this period of
setup time plus hold time, the input signal is sampled by the internal logic. The sampling point is
guaranteed to be somewhere within this time period. The input signal must be stable during this period for
it to be interpreted as a valid high or low. If it is not stable, the input circuitry will arbitrarily interpret it as a
high or a low depending on when the signal is sampled internally.
The clock pulse width, LW., defines the minimum high or low time of the clock signal for a counter or
register. It also determines the maximum frequency of the clock as equal to the the inverse of the minimum
clock period which is twice t W. For example, the 74FCT374C has a t W of 4 ns. The minimum clock period
is therefore 8 ns, and the guaranteed operating frequency is 125 MHz, minimum.
4-24 QUALITY SEMICONDUCTOR INC.
FCT-T Family Characteristics
AC test conditions are concerned with propagation delays at outputs relative to applied signals. FCT-T is
tested using industry standard test signals. Input signals transition between levels of 0.0 volts for a logic
low to 3.0 volts for a logic high with a transition time of 2.5 nanoseconds measured from the 1 0% to 90%
points of the signal transition. Rise and fall times of 1 ns are used to test minimum pulse widths such as
clock width, t W. Propagation delay is measured from the time the input crosses 1 .5 volts to the time the
output crosses 1 .5 volts. Propagation delay is tested with one output switching.
The AC test circuitry is shown below. This test circuitry is an industry standard for FCT-T logic and many
other high performance TTL logic families. Inputs under test are driven by a pulse generator with an output
impedance of 50 ohms. Outputs are loaded with 50 picofarads and 500 ohms to ground except for three
state tests. The 500 ohm resistor to ground is typically used as a part of a 1 0:1 probe for an oscilloscope
used to measure the output. The 1 0:1 probe consists of a 450 ohm resistor feeding into a 50 ohm coax
cable to the oscilloscope. This provides a 10:1 probe with no appreciable capacitive loading by the 450
ohm resistor. This is the preferred scheme for correlation to QSI test data.
Three state testing of Tplz and Tpzl modifies the test load. An additional 500 ohm resistor is switched to
+7.0 volts for these tests. This biases the output to 3.5 volts for testing the transition from high-Z to a TTL
low and from a TTL low to high-Z. The 3.5 volts is an industry standard value chosen to represent the
realistic situation of transitioning to or from a potential TTL high at the output under high-Z conditions.
500 a
VCC
o-o 7-ov
Parameter
Tested
Switch
Position
t PLZ, t PZL
Closed
All Others
Open
5 On Coax to
Oscilloscope
FCT-T Test Circuit
QUALITY SEMICONDUCTOR INC.
4-25
FCT-T Family Characteristics
AC Test Waveforms
General waveforms are shown below for testing all input to output delays. Outputs are shown for normal
and inverted signal phases, as determined by the logic function being tested. Three state disable test
waveforms are also shown, indicating the 300 millivolt change in level used to detect the high-Z condition.
3.0V
x "3V
X 1-5V
1.5V
0V
Input
Output In
Same
Phase
Output In
Opposite
Phse
0.3V
_i r ■
T
-■£ '.■
0.3V
PHZ
a >t pi ■
NOTES: 1 . For t PZH the output goes from Hi-Z to a HIGH state, and the input is a control input
2. For t PZL the output goes from Hi-Z to a LOW state, and the input is a control input
3. For t PLZ the output goes from LOW to a Hi-Z state, and the input is a control input
4. For t PHZ the output goes from HIGH to a Hi-Z state, and the input is a control input
FCT-T Test Waveforms
■
QUALITY SEMICONDUCTOR INC.
QSFCT2952T, 2953T2052T, 2053T
Q
High Speed CMOS
8-bit Bus Interface
Register Transceivers
—
QS29FCT52T
QS29FCT53T
QS29FCT2052T
QS29FCT2053T
FEATURES/BENEFITS
Pin and function compatible to the Am2952/3
29FCT52/3 and 29FCT52/3T
CMOS power levels: <7.5 mW static
Available in PDIP, ZIP, SOIC, QSOP, CERDIP • Military product compliant to MIL-STD-883
Undershoot clamp diodes on all inputs
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
FCT-T 2952T, 2953T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• A, B and C speed grades with 5.5ns tPD for C
• lol = 64 mA Com., 48 mA Mil.
— — — — — — — —
FCT-T 2052T, 2053T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• A, B and C speed grades with 5.5ns tPD for C
speed guaranteed with 50pF loads
DESCRIPTION
The QS29 FCT52T/3T are 8-bit high-speed CMOS TTL-compatible registered bus transceivers with
three-state outputs that are ideal for driving high capacitance loads such as memory and address buses.
The 2052/3 devices are 25£1 resistor output versions useful for driving transmission lines and reducing
system noise. The 2052/3 series parts can replace the 2052/3 series to reduce noise in an existing
design. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground
bounce suppression, and will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
A BUS
FCT2xxx only
REGISTER ^
A BUS
FCT2xxx only
BBUS
D CEA"
■
<
+ CPA
n
2953 only.
2952 outpute
rJEB
BBUS
QUALITY SEMICONDUCTOR INC.
4-27
QSFCT2952T, 2953T, 2052T, 2053T
PINOUTS
PDIP, SOIC, QSOP
B7 C
B6 C
B5 C
B4 C
B3 C
B2 C
B1 C
BO C
OEB C
CPA C
CEX C
GND □
1
2
3
^
5
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
□ VCC
□ A7
□ A6
□ A5
□ A4
□ A3
□ A2
□ A1
□ AO
□ QEA"
□ CPB
□ CEB
m <o i-» o 8 Is-
m m m z> <
to
<
n w --
B4 I
JS
B3 I
1 6
B2 I
1 7
NCI
1 8
T-
1 9
BO I
1 10
OEBI
H 11
CM CO
CD CO (D CD qOO<<<< >
cm •* (O eo o cm
zfp ■
y- CO IO h»
■ hi tu tu < < < <
co co rn m m ui
PIN DESCRIPTIONS
< K Q o ttl CD W
CL B Z Z UJ 0. Ill
O IO O K-> O IO
ALL PINS TOP VIEW
Name
I/O
Description
A7-A0
I/O
A Bus
B7-B0
I/O
B Bus
CPA
Register A Clock Input
CPB
Register B Clock Input
CES
Register A Clock Enable
CEB
Register B Clock Enable
OEA
Output Enable, Reg A to A Bus
DEB
Output Enable, Reg B to B Bus
■
4-28
QUALITY SEMICONDUCTOR INC.
QSFCT2952T, 2953T2052T, 2053T
FUNCTION TABLES - QS29FCT52/3, 2052/3
Inputs
Outputs
CPA
CPB
CEA"
CEB
CEA
SEB
A1-8
B1-8
X
X
X
X
H
L
Z
Breg
X
X
X
X
L
H
Areg
Z
X
X
X
X
H
H
Z
Z
X
X
X
X
L
L
Areg
Breg
1
-
Inputs
Registers
CPA
CPB
CEA"
CEB
A1 -8
B1-8
X
X
H
H
Hold
Hold
T
X
L
H
Load
Hold
X
T
H
L
Hold
Load
X
T
L
L
X
Load
T
X
L
L
Load
X
T = Low to High Transition
H =HIGH
L = LOW,
Z = High Impedance
X =Don1Care
QUALITY SEMICONDUCTOR INC. 4-29
QSFCT2952T, 2953T, 2052T, 2053T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with Vt<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature -65° to +165°C
■
CAPACITANCE
TA = 25°C, f = 1 MHz,Vin = 0V,Vout = 0V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
4
4
5
7
PF
6
6
7
9
PF
1-11,13-23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QSFCT2952T, 2953T2052T, 2053T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unl
t
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volt
5
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
I lih I
i i
111
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
uA
IkBl
Off State Output
Current (Hi-?
Vcc MAX, 0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX,Vo = GND(2,3)
-60
mA
lor
Current Drive
FCT2XXX (25Q)
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (2K2)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
£1
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate VCC-5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
rwvvcn ourru i imumv i i_i
■ . —
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Vcc = MAX, Vin =3.4 V, treq = 0 (2)
-
2.0
Input @ TTL HIGH
Qccd
Vcc = MAX, Outputs open and enabled
0.25
mN
Supply Current per
input per mHz
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
MHz
1 . For conditions shown as MIN or MAX use the <
) values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-32
QUALITY SEMICONDUCTOR INC.
QSFCT2952T, 2953T2052T, 2053T
===^=
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(D
2952/3A
292052A
292053A
2952/3B
292052B
292053B
2952/3C
292052C
292053C
Unit
Min
Max
Min
Max
Min
Max
tPHL
t PLH
Propagation Delay
Com
2
10
2
6.5
2
5.8
ns
CP to Ai.Bi, 52/3
Mil
2
11
2
7.2
0
6.8
Propagation Delay
Com
2
10
2
6.5
2
5.8
CP to Ai.Bi. 2052/3
MM
2
11
2
7.2
0
6.8
tPZH
Output Enable Time
Com
1.5
10.5
1.5
6.5
1.5
6.5
tPZL
OE to Ai.Bi. 52/3
Mil
1.5
13
1.5
7.5
1.5
7.5
Output Enable Time
Com
1.5
10.5
1.5
7.0
1.5
7.0
OE to Ai.Bi, 2052/3
Mil
1.5
13
1.5
7.5
1.5
7.5
tPHZ
Output Disable Time
OE to Ai.Bi
Com
2
2
10
2
5.5
1.5
5.5
tPLZ
Mil
2
11
2
6.5
1.5
6.5
ts
Data Setup Time
Com
2
2
2
Ai.Bi to CP
Mil
2.5
2
2
tH
Data Hold Time
Ai.Bi to CP
Com
2
1.5
1.5
Mil
2
1.5
1.5
tSCE
Clock Enable Setup
Com
2
2
2
Time, CE to CP
Mil
2
2
2
t HCE
Clock Enable Hold
Com
2
2
2
Time, CE to CP
Mil
2
2
2
tw
Clock Pulse Width
HIGH or LOW
Com
3
3
3
Mil
3
3
3
Notes:
1) See Test Circuit and Waveforms. Minimums Guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
QSFCT2952T, 2953T, 2052T, 2053T
—
1
■
■
QUALITY SEMICONDUCTOR INC.
QSFCT29520T, 29521 T, 2520T, 2521 T
-
=
Q
High Speed CMOS
Multilevel Pipeline
Registers
QS29FCT520T
QS29FCT521T
QS29FCT2520T
QS29FCT2521T
FEATURES/BENEFITS
• Pin and function compatible to the Am29520
° Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
I
FCT-T520T/1T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std , A, B & C speed grades with 6ns tPD for C
• lol = 48 mA Com., 32 mA Mil.
■ TTL-compatible input and output levels
• CMOS power levels: <7.5 mW static
• Undershoot clamp diodes on all inputs
• Military product compliant to MIL-STD-883
FCT-T 2520T/1T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• Std, A and B speed grades with 7.5ns tPD for B
lol = 12mA Com.
DESCRIPTION
The QS29FCT520AT/BT and QS29FCT521 AT/BT provide four 8-bit registers useful for temporary
storage and for stage delays in pipelined systems. The four registers may be configured as a dual 2-level
or single 4-level shift register pipeline. A single 8-bit input is provided, and any of the four registers may
be selected for gating to the single 8-bit output. The 520 and 521 differ only in how the registers are
loaded in the dual 2-rank mode, as shown in the function tables. The QS29FCT520/1 are pin and
function compatible with the Am29520/1 bipolar parts, except for higher speed and significantly lower
power.
=
FUNCTIONAL BLOCK DIAGRAM
D0-D7
Y0-Y7
QUALITY SEMICONDUCTOR INC.
PINOUTS
PDIP, SOIC, QSOP
o
O o O o
ZD ^ O > (/) W
I O § £
t- eo U)
si Q
in co i- *- O
>■ >- >- W >
t- CO U)
ZIP
_ CO U> Is- O)
<7> T- T- T— T— T—
3
o
* g I g * * s
25 C
L NC
24 C
L Y0
23 C
L Y1
22 C
?Y2
21 C
L Y3
20 C
L Y4
19C
L Y5
PIN DESCRIPTIONS
Name
I/O
Function
D0-D7
I
Data Inputs
Y0-Y7
0
Data Outputs - Three State
10, 11
I
Register Load Control
SO, S1
I
Register Output Select
CLK
I
Clock Pulse
UE
I
Output Enable
QUALITY SEMICONDUCTOR INC.
QSFCT29520T, 29521 T, 2520T, 2521 T
FUNCTION TABLES - QS29FCT520/1 , 2520/1
REGISTER LOAD CONTROL
, , ,
PART
Register Control Code
NO
11,0 =
LL = 0
I1,0 = LH = 1
11 ,0 = HL = 2
I1,0 = HH = 3
*
FCT520
A1
+
| A1 | | B1
A1 B1
Hold
t
Data
I 82 I
I A2 I I 62 I
I A2 I I 82 I
i
FCT521
A1
| A1 | | B1
[__A1_J | B1 |
Hold
Data
B2 |
| A2 | | B2
A2 B2
REGISTER OUTPUT SELECTION
S1
SO
DE
Yl
Register to Y0-Y7
L
L
L
Data
B2
L
H
L
Data
B1
H
L
L
Data
A2
H
H
L
Data
A1
X
X
H
Hi-Z
Outputs Disabled
QUALITY SEMICONDUCTOR INC.
4-37
QSFCT29520T, 29521T, 2520T, 2521 T
ABSOLUTE MAXIMUM RATINGS
83 JR.- I MO!
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25°C, f = 1 MHz, Vin =
2A
0V, Vout = 0 V
,LCC
Pins
SOIC
QSOP PDIP,
ZIP
Unit
1-11.13,22,23
4
PF
14-21
PF
8
10
PF
Note: Capacitance is characterized but not tested
<iA
4-38
QUALITY SEMICONDUCTOR INC.
QSFCT29520T, 29521 T, 2520T, 2521 T
============================================
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5 0V±5% Military TA=-55°C to 1 25°C, Vcc=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
—
Unit
Input High Voltage
Logic HIGH for All Inputs
2.0
Volt!
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
0.2
lih
I lil I
Input Current
Input HIGH or LOW
Vcc = MAX
' i
0 < Vin < Vcc
-
-
5
uA
|loz|
Off State Output
Current (Hi-Z)
Vcc = MAX, 0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
.
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
loU 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25fl)
Vcc = MIN
bl = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (2K2)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol= 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-39
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
KC
uuiescem rower
Supply Current
\/~~ _ HAV f ran — f\
vcc — mma, ireq = u
0V<Vin^0.2V or Vcc-0.2V<Vin<Vcc
mA
AlCC
Supply Current per
Input® TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
-
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mAJ
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-40
—
QUALITY SEMICONDUCTOR INC.
QSFCT29520T, 29521T, 2520T, 2521 T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCc=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(1)
29FCT
520/1A
2520/1A
29FCT
520/1 B
2520/1 B
29FCT
520/1 C
2520/1C
Unit
Mln
Max
Mln
Max
Mln
Max
tCPD
Clock to Y Delay
COM
2
14
2
7.5
2
6
MIL
2
16
2
8
2
7
t DY
S0.1 to Y Delay
COM
5
13
2.5
7.5
2
6
MIL
6
15
2
8
2
7
tDS
Data to CLK Setup Time
COM
5
2.5
2.5
MIL
6
2.8
2.8
tDH
Data to CLK Hold Time
COM
2
2
2
ns
MIL
2
2
2
t IS
10,1 to CLK Setup Time
COM
S
4
4
MIL
6
4.5
4.5
tlH
10,1 to CLK Hokt Time
COM
2
2
2
MIL
2
2
2
toz
Output Disable Time
OEtoY
COM
2
1.5
12
1.5
7
1.5
6
MIL
1.5
13
1.5
7.5
1.5
6
tOE
Output Enable Time
OEtoY
COM
1.5
15
1.5
7.5
1.5
6
MIL
1.5
16
1.5
8
1.5
7
tew
CLK Pulse Width,
High or Low
COM
2
7
5.5
5.5
MIL
8
6
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-41
QSFCT29520T, 29521 T, 2520T, 2521 T
-
-
)C8 ! M OSS '
! s .
■
■
— — — — — — ^— — —
QUALITY SEMICONDUCTOR INC.
QS74FCT138T, QS74FCT238T
Q
High Speed CMOS
1-of-8 Decoders
QS54/74FCT138T
QS54/74FCT238T
FEAT
TS
• QSFCT138A faster than 74F
• lol=48 mA COM , 32 mA M IL
• TTL-compatible input and output levels
• Mil product compliant with MIL-STD 883, Class B
—
DESCRIPTION
• QSFCT238T has positive active outputs
• CMOS power levels < 7.5 mW static
• Available in PDIP, ZIP, SOIC, CERDIP, LCC
• JEDEC standard pinouts
-
The QSFCT138T and QSFCT238T are high speed CMOS TTL-compatible high speed binary
decoders. The QSFCT138T has negative active outputs, and the QSFCT238T has positive active
outputs. The high output current lol and loh drive high capacitance loads. All inputs have clamp diodes
for undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001 ), and outputs will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
AO A1 A2 ET E2 E3
Inverting Outputs on 138 Only
(Non-inverting outputs on 238)
— —
QUALITY SEMICONDUCTOR INC.
4-43
QS74FCT138T, QS74FCT238T
PIN CONFIGURATIONS
PDIP, SOIC
vcc
■ <.'J
INDEX ;§^B
A2Z
m
1 4
CM t-
8 2
18
etS
1 5
17
NClI
E2J
1 6
LCC
16
] 7
15
E3J
1 8
O i-
«. co14
cn ■»-■»- t-
ALL PINS TOP VIEW
For ZIP pinout contact factory.
Name
I/O
Description
Ai
I
Select Inputs
Oi
O
Decode Outputs
Ei
I
Enable
lo B
Output
Output
Level
State
1 38
238
0
H
L
1
L
H
Enable
Select
Output
Function
ET
E2
E3
A2
A1
AO
07
06
OS
04
03
02
01
oo
H
X
X
X
X
X
0
0
0
0
0
0
0
0
Disable
X
H
X
X
X
X
0
0
0
0
0
0
0
0
Disable
X
X
L
X
X
X
0
0
0
0
0
0
0
0
Disable
L
L
H
L
L
L
0
0
0
0
0
0
0
1
A2-0 = 0
L
L
H
L
L
H
0
0
0
0
0
0
1
0
A2-0 = 1
L
L
H
L
H
L
0
0
0
0
0
1
0
0
A2-0 = 2
L
L
H
L
H
H
0
0
0
0
1
0
0
0
A2-0 = 3
L
L
H
H
L
L
0
0
0
1
0
0
0
0
A2-0 = 4
L
L
H
H
L
H
0
0
1
0
0
0
0
0
A2-0 = 5
L
L
H
H
H
L
0
1
0
0
0
0
0
0
A2-0 = 6
H
H
H
H
1
0
0
0
0
0
0
0
A2-0 = 7
QUALITY SEMICONDUCTOR INC.
m
QS74FCT138T, QS74FCT238T
ABSOLUTE MA
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-3
4
4
5
7
PF
7,9-12
6
6
7
9
PF
4-6,13-15
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY SEMICONDUCTOR INC. 4-45
QS74FCT138T, QS74FCT238T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCc=50V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
\m\
I lill
Input Current
Incut HIGH or LOW
Vcc= MAX
0 < Vin < Vcc
-
-
5
uA
|taz|
Off State Output
Current <Hi-Z)
V/UI 1 VI *\ \l m * — f
Vcc = MAX,0<Vin<Vcc
■
■
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
-
— > —
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
- -
-
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lot = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (2K1)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1. Typical values indicate Vqq=5.0V and TA-25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-46 QUALITY SEMICONDUCTOR INC.
QS74FCT138T, QS74FCT238T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V^Vin^0.2V or Vcc-0.2V^Vin^Vcc
1.5
mA
AlCC
Supply Current per
Input® TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc - 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(D
138, 238
138A
238A
138C
238C
138D
238D
Unit
ns
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
AitoOi
COM
1.5
9
1.5
5.8
1.5
5.0
1.0
4.0
MIL
1.5
12
1.5
7.8
1.5
7.0
tPHLE
tPLHE
Propagation Delay
EitoOi
COM
1.5
8
1.5
5.9
1.5
5.0
1.0
4.0
MIL
1.5
12
1.5
8.0
1.5
7.0
Notes:
1 . See test circuits and wave forms.
2 . This parameter is guaranteed but not tested.
i
QUALITY SEMICONDUCTOR INC.
4-47
QS74FCT138T, QS74FCT238T
■ ■
■
4-48
QSFCT139T, 239T
Q
High Speed CMOS
Dual Binary
1-of-4 Decoders
QS54/74FCT139T
QS54/74FCT239T
FEATURES/BENEFITS
=
• QSFCT139D with 4.0 ns prop, delay
• lol=48 mA COM, 32 mA MIL
> TTL-compatlble Input and output levels
• Mil product compliant with MIL-STD 883, Class B
• QSFCT239T has positive active outputs
• CMOS power levels < 7.5 mW static
• Available in PDIP, ZIP, SOIC, CERDIP, LCC
• JEDEC standard pinouts
DESCRIPTION
The QSFCT139T and QSFCT239T are high speed CMOS TTL-compatible high speed binary
decoders. The QSFCT139T has negative active outputs, and the QSFCT239T has positive active
outputs. The high output current lol and loh drive high capacitance loads. All inputs have (
for undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001), and outputs will not load an active bus when Vcc is removed from f
FUNCTIONAL BLOCK DIAGRAM
A1a"P=
OOi
Inverting Outputs on 139 Only
(Non-inverting outputs on 239)
4-49
i
QSFCT139T, 239T
—
PIN CONFIGURATIONS
ALL PINS TOP VIEW
For ZIP pinout
PIN DESCRIPTION AND FUNCTION TABLE
Name
I/O
Description
Ai
I
Select Inputs
Oi
0
Decode Outputs
Ei
I
Enable
Output
State
Output Level
139
239
0
H
L
1
L
H
Enable
Select
Output
Notes
Ei," EE
A1
AO
03
02
01
oo
H
X
X
0
0
0
0
Disable Decode
L
L
L
0
0
0
1
A1-0 = 0
L
L
H
0
0
1
0
A1-0 = 1
L
H
L
0
1
0
0
A1-0 = 2
L
H
H
1
0
0
0
A1-0 = 3
QSFCT139T, 239T
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation ••> • .0.5 watts
-65°to+165°C
CAPACITANCE
, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1 3
4
4
5
7
PF
7,9-12
6
6
7
9
PF
4-6,13-15
8
9
10
PF
8
is characterized but not tested
QUALITY SEMICONDUCTOR INC.
4-51
QSFCT139T, 239T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
VOIT5
Ml
VII
Inni it 1 HW VrtHaria
input LuW VOIldyc
Logic LOW for All Inputs
u.o
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
I* I
HI
Input Current
Input HIGH or LOW
Vcc = MAX
0 <, Vin < Vcc
5
UA
|bz|
Off State Output
Current (Hi-Z)
Vcc=MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25fl)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25£i)
Vcc = MIN
lol = 12 mA (MIL)
21 | 28
38
Q
lol = 12 mA (COM)
24 | 28
35
Notes : 1 . Typical values indicate Vqc=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-52
QUALITY SEMICONDUCTOR INC.
QSFCT139T, 239T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
tec
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin^Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(1)
139, 239
139A
239A
139C
239C
139D
239D
Unit
ns
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to Oi
COM
1.5
9
1.5
5.8
1.5
5.0
1.0
4.0
MIL
1.5
12
1.5
7.8
1.5
7.0
tPHLE
tPLHE
Propagation Delay
EitoOi
COM
1.5
9
1.5
5.9
1.5
5.0
1.0
4.0
MIL
1.5
12
1.5
8.0
1.5
7.0
Notes:
1 . See test circuits and wave forms.
QUALITY SEMICONDUCTOR INC.
4-53
QSFCT139T, 239T
-
■
4-54
QUALITY
JTOR INC.
QSFCT151T, 251 T, 2152T, 2251 T
Q
QS54/74FCT151T
High-Speed CMOS qs54/74fct25it
8 Input
Multidexers qs54/74fct2isit
iviumpiexers qs54/74FCT2251T
FEATURES/BENEFITS
• Pin and function compatible to the 74F1 51/251
74FCT1 51/251 and 74FCT151T/251T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 151T, 251T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Standard and A speed grades with 5.2ns tPD for A
• lol = 48 mA Com., 32 mA Mil.
DESCRIPTION
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3 .5V
• Military product compliant to MIL-STD-883
FCT-T 2151T, 2251 T
• Built-in 25£2 series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 5.2ns tPD for A
• lol = 12mA Com.
=
The QSFCT151T and QSFCT251T are high speed CMOS TTL-compatible 8-input multiplexers. The
151 has TTL outputs; the 251 has 3-state outputs. The QSFCT2151T and QSFCT2251T are 25Q
resistor output versions useful for driving transmission lines and reducing system noise. All inputs have
clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression (see
QSI Application Note AN-001). Outputs will not load an active bus when Vcc is removed from the
device.
FUNCTIONAL BLOCK DIAGRAM
E S2 S1 SO 10 11 12 13 14 15 16 17
3-State Enable on 251/2251 Only
/ a
s *
\ to
FCT2xxx
only
win iMwiinnwiW
PDIP, SOIC, QSOP
INDEX
n !I
3 4
lOl
1 5
NClI
3 6
Y?
] 7
Yl
3 8
ALL PINS TOP VIEW
* For ZIP pinout call factory
■
w § g « »
MOIT<llfl^
■
PIN DESCRIPTION
FUNCTION TABLE
Name
I/O
Description
E
Select
1 51
251
Function
10-7
1
Data Inputs
S2
S1
SO
Y
Y
Y
Y
S0-2
1
Select Inputs
H
X
X
X
H
L
Hl-Z
Hl-Z
Disable
E
1
Enable
L
L
L
L
10
15
10
10
S2-0 = 0
y/y
0
Data Outputs
L
L
L
H
11
IT
11
TT
S2-0 = 1
L
L
H
L
12
15
12
15
S2-0 = 2
L
L
H
H
13
13
13
T5
S2-0 = 3
L
H
L
L
14
14
14
14
S2-0 = 4
L
H
L
H
15
15
15
15
S2-0 = 5
L
H
H
L
16
16
16
15
S2-0 = 6
L
H
H
H
17
17
17
17
S2-0 = 7
4-56
QUALITY SEMICONDUCTOR INC.
QSFCT151T, 251 T, 2152T, 2251 T
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
- '
| Ml |
I I'l I
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
-
-
5
HA
|loz|
Off State Output
Current (Hi-Z)
Vcc=MAX,0<Vin<Vcc
_
_
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-BO
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
_
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
■
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
loU 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
bl = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
k>l = 12 mA (MIL)
21
28
38
a
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc-S.OV and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
=
4-58
QSFCT151T, 251 T, 2152T, 2251 T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc=MAX,Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipf lops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMICONDUCTOR INC.
4-59
QSFCT151T, 251 T, 2152T, 2251 T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500n unless otherwise noted
Symbol
I 1
Description
Notes
(1 )
151
251
2151
2251
151 A
251A
21 51 A
2251A
Unit
Min
Max
Min
Min
Mnv
■VI OA
t IY
Propagation Delay
In to Y or Y. 151/251
COM
1 -O
"7
f
1 .0
ns
14 11
MIL
1 .3
Q
O
1 .0
O.O
Propagation Delay
In to Y or Y, 2151/2251
COM
1 -D
■7
1 .0
MIL
1 .5
O
O
1 .0
tSY
Propagation Delay
SntoYor Y, 151/251
COM
1 .o
y
1 c
1 -D
0.0
Ml L
i .5
0 c
1 .0
f .4
r rupayauuit uoldy
Sn to Y or Y, 2151/2251
COM
\j no
y
1 .0
D.D
MIL
1 .5
9.5
1.5
7.4
tOEH
tOEL
Output Enable Time
EtoYi, 151
COM
1.5
7
1.5
5.2
MIL
1.5
8
1.5
5.8
Output Enable Time
EtoYi, 2151
COM
1.5
7
1.5
5.2
MIL
1.5
8
1.5
5.8
tPZH
tPZL
Output Enable Time
EtoYi, 151/251
COM
1.5
9
1.5
6.0
MIL
1.5
10
1.5
6.4
Output Enable Time
EtoYi. 2151/2251
COM
1.5
9
1.5
6.0
MIL
1.5
10
1.5
6.4
tPHZ
tPLZ
Output Disable Time
EtoYi, 251/2251
COM
2
1.5
7
1.5
6
MIL
2
1.5
7
1.5
6.3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-60
QUALITY SEMICONDUCTOR INC.
QSFCT153T, 253T, 2153T, 2253T
Q
..■ ^ « QS54/74FCT153T
High-Speed CMOS QS54/74FCT253T
Dual 4 Input
MllltinlPYPr<% QS54/74FCT2153T
Multiplexers QS54/74FCT2253T
FEATURES/BENEFITS
• Pin and function compatible to the 74F1 53/253
74FCT1 53/253 and 74FCT153T/253T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 153T, 253T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Standard and A speed grades with 5.2 ns tPD for A
• lol = 48 mA Com., 32 mA Mil.
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Military product compliant to MIL-STD-883
FCT-T 2153T, 2253T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 5.2 ns tPD for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT153T and QSFCT253T are high speed CMOS TTL-compatible dual 4-input multiplexers.
The 153 has TTL outputs; the 253 has 3-state outputs. The QSFCT21 53T and QSFCT2253T are 25Q
resistor output versions useful for driving transmission lines and reducing system noise. All inputs have
clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression (see
QSI Application Note AN-001). Outputs will not load an active bus when Vcc is removed from the
device.
FUNCTIONAL BLOCK DIAGRAM
EB EA S1 SO I0A MA I2A I3A IOB MB I2B I3B
YA YB
QUALITY SEMICONDUCTOR INC.
4-61
QSFCT153T, 253T, 2153T, 2253T
PIN CONFIGURATIONS
PDIP, SOIC, QSOP
GND
GNDC 8
□ 11 B
□ IOB
□ YB
ALL PINS TOP VIEW
* For ZIP pinout call factory
m
PIN DESCRIPTION
FUNCTION TABLE
Name
I/O
Description
I0-7
I
Data In
SO-1
I
Select
E5.'EB
I
Enable
YA, YB
0
Data Out
Enable
Select
153
253
Function
ES
EB
S1
SO
YA
YB
YA
YB
H
X
X
X
L
X
Hi-Z
X
Disable A
X
H
X
X
X
L
X
Hi-Z
Disable B
L
L
L
L
I0A
IOB
I0A
IOB
S1-0 = 0
L
L
L
H
MA
MB
MA
MB
S1-0 = 1
L
L
H
L
I2A
I2B
I2A
I2B
S1-0 = 2
L
L
H
H
I3A
I3B
I3A
I3B
S1-0 = 3
QUALITY
QSFCT153T, 253T, 2153T, 2253T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Numberof Outputs, M=Numberof inputs
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature
-65°to+165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-6,10-15
4
4
5
7
pF
7,9
6
6
7
9
PF
8
8
9
10
pF
■
QUALITY SEMICONDUCTOR INC.
4-63
QSFCT153T, 253T, 2153T, 2253T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
-
|Hh|
I lii I
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
u.A
|taz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
CPTWV
rO 1 AAA
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
lor
Current Drive
rO 1 tAAA
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin= 18 mA (3)
-0.7
-1.2
Volts
von
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
voits
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
VCC = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (2K2)
VCC = MIN
loU 12 mA (MIL)
0.50
lol = 12rnA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
VCC = MIN
loU 12 mA (MIL)
21
28
38
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
QSFCT153T, 253T, 2153T, 2253T
—
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2VsVin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4 V)
3. For f lipf lops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMICONDUCTOR INC.
QSFCT153T, 253T, 2153T, 2253T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
i —
Description
Notes
(1)
153
253
2153
2253
153A
253A
21 53 A
2253A
Unit
Min
Max
Min
Max
1.5
5.2
t IY
Propagation Delay
IntoY, 153/253
COM
1.5
7
ns
MIL
1.5
8
1.5
5.8
Propagation Delay
IntoY, 2153/2253
COM
1.5
7
1.5
5.2
8
1.5
5.8
MIL
1.5
tSY
Propagation Delay
Snto Y, 153/253
COM
1.5
9
1.5
6.6
MIL
1.5
9.5
1.5
7.4
Propagation Delay
Sn to Y, 2153/2253
COM
1.5
9
1.5
6.6
MIL
1.5
9.5
1.5
7.4
tOEH
tOEL
Output Enable Time
EtoYi, 153
COM
1.5
7
1.5
5.2
MIL
1.5
8
1.5
5.8
Output Enable Time
EtoYi, 2153
COM
1.5
7
1.5
5.2
MIL
1.5
8
1.5
5.8
tPZH
tPZL
Output Enable Time
EtoYi, 253
COM
1.5
9
1.5
6.0
MIL
1.5
10
1.5
6.4
Output Enable Time
EtoYi, 2253
COM
1.5
9
1.5
6.0
MIL
1.5
10
1.5
6.4
tPHZ
tPLZ
Output Disable Time
E to Yi, 253/2253
COM
2
1.5
7
1.5
6
MIL
2
1.5
7
1.5
6.3
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
=
4-66
QUALITY SEMICONDUCTOR INC.
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
Q
High-Speed CMOS
Quad 2 Input
Multiplexers
QS54/74FCT157T
QS54/74FCT158T
QS54/74FCT257T
QS54/74FCT258T
QS54/74FCT2157T
QS54/74FCT2158T
QS54/74FCT2257T
QS54/74FCT2258T
FEATURES/BENEFITS
• Pin and function compatible to the 74F1/257/8
74FCT 1/257/8 and 74FCT1/257/8T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 157T, 158T, 257T, 258T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A and C speed grades with 4.3 ns for C
• lol = 48 mA Com., 32 mA Mil.
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Military product compliant to MIL-STD-883
FCT-T 2157T, 2158T, 2257T, 2258T
• Built-in 25a series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 5.0 ns for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT157T/8T and QSFCT257T/8T are high speed CMOS TTL-compatible 8-input multiplexers.
The 157/257 parts are non-inverting; the 158/258 are inverting. The 157/8 has TTL outputs; the 257/8
has 3-state outputs. The QSFCT21 57T/8T and QSFCT2257T/8T are 25Q resistor output versions
useful for driving transmission lines and reducing system noise. All inputs have clamp diodes for
undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001). Outputs will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
S I0A HA |0B MB IOC I1C I0D I1D
3-State Enable
on 257/8,
2257/8 Only
Inverting Outputs
on 158/258,
2158/2258 Only
FCT2xxx only
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
PIN CONFIGURATIONS
PDIP, SOIC, QSOP
INDEX
<
o
o
o
o
> UJ
ALL PINS TOP VIEW
* For ZIP pinout call factory
PIN DESCRIPTION
Name
I/O
Description
Ixx
I
Data Inputs
S
I
Select Input
E
I
Enable Input
YA-YD
0
Data Outputs
FUNCTION TABLES
E
S
157
I 1
158
l 1
Function
YA
YB
YC
YD
YA
YB
YC
YD
H
X
L
L
L
L
H
H
H
H
Disable
L
L
I0A
I0B
IOC
I0D
I0A
I0B
IOC
I0D
Select 0
L
H
MA
MB
11 c
I1D
MA
MB
MC
MD
Select 1
E
S
257
258
Function
YA
YB
YC
YD
YA
YB
YC
YD
H
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Disable
L
L
I0A
I0B
IOC
I0D
IOA
IOB
T5C"
100
Select 0
L
H
MA
MB
I1C
11 D
MA
MB
TTC
MD
Select 1
4-68
QUALITY SEMICONDUCTOR INC.
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TsxGStorage Temperature -65° to +165°C
:
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-3,5,6,10,11,13-15
4
4
5
7
PF
4,7,9,12
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
=
QUALITY SEMICONDUCTOR INC.
4-69
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test
Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
-
Volts
Vil
InDut LOW Voltaae
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
-
I lih I
|1|
InDut Current
1 1 IwU I VJ 1 1 TIL
Input HIGH or LOW
Vcc = MAX
0 <, Vin < Vcc
-
5
uA
I toz I
Off State OutDut
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc =
Min, Vo =2.0V
50
mA
Vic
-0.7
-1.2
Volts
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
Voh
Output HIGH Voltage
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
FCTXXX & FCT2XXX
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
VCC = MIN
lol = 32 mA (MIL)
0.50
FCTXXX
lol = 48 mA (COM)
0.50
Output LOW Voltage
Vcc=MIN
lol = 12 mA (MIL)
0.50
FCT2XXX (25£2)
lol = 12 mA (COM)
0.50
Rout
Output Resistance
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
FCT2XXX (25£2)
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq-5.0V and T^=25"C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-70
QUALITY SEMICONDUCTOR INC.
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 .5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For f lipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMICONDUCTOR INC.
QSFCT157/8T, 257/8T, 2157/8T, 2257/8T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
157/8
257/8
157/8A
257/8A
157/8C
Unit
(1)
2157/8
2257/8
2157/8A
2257/8A
257/8C
Mm
Max
V Jin
Mm
Max
Mm
Max
tlY
Propagation Delay
Into Y, 157/8/257/8
COM
1.5
6.0
1.5
5.0
1 .5
4.3
ns
Mil
MIL
1 .5
T n
/.0
1 .5
5.8
1 .5
5.0
Propagation Delay
In to Y, 2157/8/2257/8
1.5
6.0
1 .5
5.0
Mil
MIL
1.5
7.0
1 .5
5.8
tSY
Propagation Delay
StoY. 157/8/257/8
COM
1 .5
10.5
1 .5
7.0
1.5
5.2
MIL
1 .0
1 o
i£.
1 .o
O. I
1 c
1 .t>
b.U
Propagation Delay
StoY, 2157/8/2257/8
COM
1.5
10 5
1.5
7.0
MIL
1.5
12
1.5
8.1
tOEH
tOEL
Output Enable Time
EtoYi, 157/8
COM
1.5
10.5
1.5
6.0
1.5
4.8
MIL
1.5
12
1.5
7.4
1.5
5.9
Output Enable Time
EtoYi, 2157/8
COM
1.5
10.5
1.5
6.0
MIL
1.5
12
1.5
7.4
tPZH
tPZL
Output Enable Time
EtoYi, 257/8
COM
1.5
8.5
1.5
7.0
1.5
6.0
MIL
1.5
10
1.5
8.0
1.5
6.8
Output Enable Time
Eto Yi, 2257/8
COM
1.5
8.5
1.5
7.0
MIL
1.5
10
1.5
8.0
tPHZ
tPLZ
Output Disable Time
EtoYi, 257/8/2257/8
COM
2
1.5
6.0
1.5
5.5
1.5
5.0
MIL
2
1.5
8.0
1.5
5.8
1.5
5.3
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
QSFCT161T, 2161T, 163T, 2163T
Q
High-Speed CMOS
Synchronous Presettable
4-Bit Binary Counters
FEATURES/BENEFITS
QS54/74FCT1 61T
QS54/74FCT163T
QS54/74FCT2161T
QS54/74FCT2163T
—
• Pin and function compatible to the 74F1 61/3
74FCT 161/3 and 74FCT1 61 T/3T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 161T, 163T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std., A and C speed grades with 5.6 ns tPD for C
■ lol = 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2161T, 2163T
Built-in 25£2 series resistor outputs reduce
reflection and other system noise
Std and A speed grades with 6.2 ns tPD for A
lol = 12mA Com.
DESCRIPTION
The QSFCT161T and QSFCT163T are high speed CMOS synchronous presettable 4-bit binary
counters. The 1 61 has an asynchronous clear; the 1 63 has a clocked synchronous clear. The 21 61
and 21 63 are 25Q resistor output versions of the 1 61 and 1 63, respectively, and are useful for driving
transmission lines and reducing system noise. Data is preloaded or the counters count on the rising
edge of the clock. Count enable inputs and terminal count outputs allow these counters to be
cascaded without loss of speed. Preset inputs override count inputs, and clear inputs override both
preset and count inputs. All inputs have clamp diodes for undershoot noise suppression. All outputs
have ground bounce suppression (see QSI Application Note AN-001).
FUNCTIONAL BLOCK DIAGRAM
CET
)
25ft
TC
FCT2xxx only
Q0-Q3
161 Only
QUALITY SEMICONDUCTOR INC.
4-73
QSFCT161T, 2161T, 163T, 2163T
PIN CONFIGURATIONS
PDIP, SOIC, QSOP
(^□prV^TTh vcc
cpC 2
DO C 3
gndC
DIE
4
13
02 C
5
12
D3C
6
11
15 1TC
H Uoo
□ Q1
□ Q2
10 □
9 HFC
3^1
ALL PINS TOP VIEW
•ForZIPpinout call factory
■
-
INDEX o
UJ
0- Q O
UJ
o
4-74
QUALITY SEMICONDUCTOR INC.
QSFCT161T, 2161T, 163T, 2163T
PIN DESCRIPTION
Name
I/O
Description
Name
I/O
Description
DO-3
I
Data Inputs
CEP
I
Count Enable
QO-3
0
Data Outputs
CET
I
Count and TC Enable
CP
I
Clock
TC
o
Terminal Count
MR
I
Master Reset
PE
I
Parallel Load Enable
FUNCTION TABLE
Inputs
Outputs
Function
MR
PE
CP
CEP
CET
Di
QO-3
TC
161
163
L
X
X
X
X
X
L
L
Clear 161
L
X
t
X
X
X
L
L
Clear 163
H
L
T
X
X
DO-3
DO-3
DO-3
X
Load Data
H
H
T
H
H
X
Q+1
Q+1
X
Count
H
H
t
L
X
X
Q
Q
X
Count Inhibit P
H
H
t
X
L
X
Q
Q
X
Count Inhibit T
H
H
X
X
H
X
F
F
H
Count =1111
H
H
X
X
H
X
0-E
0-E
L
Count * 1 1 1 1
H
H
X
X
L
X
X
X
L
TC Inhibit
■
QUALITY SEMICONDUCTOR INC.
4-75
QSFCT161T, 2161T, 163T, 2163T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature -65° to +165°C
CAPACITANCE
■
TA = 25°C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-7,9,10
4
4
5
7
PF
11-15
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
4-76
QUALITY SEMICONDUCTOR INC.
QSFCT161T, 2161T, 163T, 2163T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
VI I
input low voltage
Logic LOW for All Inputs
U.O
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
ffn|
|i|
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
3
HA
|bz|
Vcc = MAX,0<Vin<Vcc
Off State Output
Current (Hi-Z)
0
los
Short Circuit Current
r\j 1 AAA
Vcc = MAX,Vo = GND(2,3)
-60
-
-
mA
lor
Current Drive
ru 1 AAA
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin=18mA (3)
-1
Volts
v u n
wuipui niun vuiidyt;
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
0 A
Vnltc
loh= 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (2K2)
Vcc = MIN
bl = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25£i)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
a
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate V(^=5.0V and Ta,=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-77
QSFCT161T, 2161T, 163T, 2163T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
IOC
Quiescent Power
Supply Current
vec = max, treq = 0
0V<;Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 .5
mA
AlCC
Supply Current per
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2.0
Input @TTL HIGH
Vcc = MAX, Outputs open and enabled
0.25
mA/
Qccd
Supply Current per
input per mHz
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipfbps Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
net
■
■
4-78
QUALITY SEMICONDUCTOR INC.
QSFCT161T, 2161T, 163T, 2163T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
161
163
161 A
163A
161C
163C
Unit
(1)
2161
2163
2161 A
2163A
Min
Max
Min
Max
Min
Max
tCPQ
Propagation Delay
CPtoQi, 161/3
COM
2
9.5
2
6.2
2
5.6
ns
MIL
2
10
2
6.5
2
6.1
Propagation Delay
CPtoQi, 2161/3
COM
2
9.5
2
6.2
MIL
2
10
2
6.5
tMRQ
Propagation Delay
MR to Qi, 161
COM
2
13
2
8.5
2
7.8
MIL
2
14
2
9.1
2
8.3
Propagation Delay
MR to Qi, 2161
COM
2
14
2
9.1
MIL
2
13
2
8.5
tCPTC
Propagation Delay
CPtoTC
COM
2
15
2
9.8
2
8.8
MIL
2
16.5
2
10.8
2
9.8
tCETC
Propagation Delay
CETtoTC
COM
1.5
8.5
1.5
5.5
1.5
5.0
MIL
1.5
9
1.5
5.9
1.5
5.4
tMRTC
Propagation Delay
MRtoTC
COM
1.5
11.5
1.5
7.5
1.5
6.8
MIL
1.5
12.5
1.5
8.2
1.5
7.4
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC. 4-79
QSFCT161T, 2161T, 163T, 2163T
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
totes
1) See Test
2) This
Symbol
Description
Notes
161
163
161A
163A
161C
163C
Unit
(1)
2161
2163
2161 A
2163A
Min
Max
Min
Max
Min
Max
tDS
Data Setup Time
DitoCP
COM
5
4
3.5
ns
MIL
5.5
4.5
4.0
tDH
Data Hold Time
DitoCP
COM
I .O
1 e
I .o
MIL
2
2
2
tcs
Count Enab. Setup Time
CEP, CETtoCP
COM
1 1 .5
9.5
8.5
MIL
13
11
10
tCH
Count Enable Hold Time
CEP, CETtoCP
COM
o
0
0
MIL
0
0
0
tMRS
t PES
Control Setup Time
MR, PEtoCP
COM
11.5
9.5
8.5
MIL
13.5
11.5
10.5
tMRH
tPEH
Control Hold Time
"RR, PEtoCP
COM
1.5
1.5
1.5
MIL
1.5
1.5
1.5
tCPW
Clock Pulse Width
HIGH or LOW
COM
2
5
4
3
MIL
2
5
4
3
tMRW
~MH Reset Pulse Width
161,2161
COM
2
5
4
3
MIL
2
5
4
3
tMRW
Reset Recovery Time
MRtoCP, 161,2161
COM
2
6
5
4
MIL
2
6
5
4
Circuit and Waveforms. Minimums guaranteed but not tested,
is guaranteed by design but not tested.
=
4-80
QUALITY SEMICONDUCTOR INC.
QS74FCT191T, QS74FCT2191T
Q
High-Speed CMOS
Presettable Synchronous
4-Bit Binary Counters
QS54/74FCT191T
QS54/74FCT2191T
FEATURES/BENEFITS
Pin and function compatible to the 74F191
74FCT191 and 74FCT191T
CMOS power levels: <7.5 mW static
Available in PDIP, ZIP, SOIC, QSOP, CERDIP
Undershoot clamp diodes on all inputs
FCT-T 191T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A and C speed grades with 6.9ns tPD for C
• lol = 64 mA Com., 48 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2191T
• Built-in 25Q. series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 7.8ns tPD for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT191T is a high speed CMOS 4-bit binary up/down counter. It has a single clock with clock
enable and up/down control inputs and ripple carry output. The '191 has asynchronous preload inputs
which override the count inputs. The '2191 is a 25Q resistor output version of the '191 and is useful for
driving transmission lines and reducing system noise. All inputs have clamp diodes for undershoot
noise suppression. All outputs have ground bounce suppression (see QSI Application Note AN-001).
FUNCTIONAL BLOCK DIAGRAM
■
QUALITY SEMICONDUCTOR INC.
4-81
QS74FCT191T, QS74FCT2191T
—
PIN CONFIGURATIONS
PDIP, SOIC
8 § 2 S 8
ALL PINS TOP VIEW
* For ZIP pinout contact factory.
4-82
QUALITY SEMICONDUCTOR INC.
S
QS74FCT191T, QS74FCT2191T
PIN DESCRIPTION
Name
I/O
Description
DO-3
I
Data inputs
QO-3
0
Data Outputs
PC
I
Pre Load
U/D
I
Up/Down Select
CE
I
Count Enable
CP
I
Count Clock
TC
0
Terminal Count
PC
0
Ripple Clock
FUNCTION TABLE
Inputs
Outputs
PC
D/D
CP
CE
Di
QO-3
TC
PC
L
X
X
X
DO-3
DO-3
X
X
Load Data
H
L
T
L
X
Q+1
X
X
Count Up
H
H
t
L
X
Q-1
X
X
Count Down
H
X
X
H
X
Q
X
X
Count Inhibit
H
L
X
X
X
F
H
H
Count Up =1111
H
L
IT
L
X
F
H
u*
H
L
X
X
X
0-E
L
H
Count Up * 1 1 1 1
H
H
X
X
X
0
H
H
Count Dn = 0000
H
H
IT
L
X
0
H
U
H
H
X
X
X
1-F
L
H
Count Dn * 0000
i
QUALITY SEMICONDUCTOR INC.
4-83
QS74FCT191T, QS74FCT2191T
==========^=s=====s==:
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V, -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Numberof Outputs, M=Numberof inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,4,5,9-11,14,15
4
4
5
7
PF
2,3,6,7,12,13
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY SEMICONDUCTOR INC.
QS74FCT191T, QS74FCT2191T
=
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 125° C, Vcc = 5.0V±10%
Symbol
Parameter
Test Conditions
Mln
Typ
Max
Unit
(1)
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
VII
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
I I'M
I iii I
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
uA
\toz\
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
r*/K'r v/\/\/
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
*
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
VCC = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
VCC = MIN
lol = 12 mA (MIL)
21
28
38
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-85
QS74FCT191T, QS74FCT2191T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V^Vins0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2.0
Input @TTL HIGH
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
-.
QUALITY SEMICONDUCTOR INC.
QS74FCT191T, QS74FCT2191T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 125° C, Vcc = 5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(D
191
2191
Min
Max
191A
21 91 A
Min
Max
191C
Min
Max
Unit
tCPQ
tCPTC
tCPRC
tCERC
tUDRC
tUDTC
tPQ
tPLQ
Propagation Delay
CPtoQi
Propagation Delay
CPtoTC
Propagation Delay
cp to re:
Propagation Delay
CEtoRC
Propagation Delay
D/Dto"RC
Propagation Delay
O/DtoTC
Propagation Delay
PitoQi
Propagation Delay
PTtoQi
COM
2.5
12
2.5
7.8
6.9
MIL
1.5
16
1.5
10.5
1.5
COM
3.0
14
3.0
11.8
2.5
10.2
MIL
2.0
16
2.0
12.2
2.0
11.5
COM
2.5
8.5
2.5
8.5
2.0
MIL
1.5
12.5
1.5
10.0
1.5
9.2
COM
7.2
6.8
MIL
8.5
7.4
COM
15
9.8
9.0
MIL
16.5
10.8
10.0
COM
11
7.2
6.8
MIL
13
8.5
7.9
COM
14
9.1
8.5
MIL
1.5
16
1.5
10.4
1.5
9.8
COM
13
8.5
7.8
MIL
14
9.1
8.5
Notes:
1) See Test Circuit and Waveforms. Mini mums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-87
QS74FCT191T, QS74FCT2191T
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500£i unless otherwise noted
Symbol
Description
Notes
(D
191
2191
191A
21 91 A
191C
Unit
Min
Max
Min
Max
Min
Max
tPPLS
Pi to PC setup
COM
5
4
4
MIL
g
5
5
tPPLH
Pi to PC hold
COM
1.5
1.5
1.5
MIL
1.5
1.5
1.5
tCS
CETO CP setup
COM
10
9
9
MIL
10.5
9.5
9.5
tCH
CFto CP hold
COM
0
0
0
MIL
0
0
0
tUDCPS
D/D to CP setup
COM
12
10
10
MIL
12
10
10
tUDCPH
U/DtoCPhold
COM
0
0
0
MIL
0
0
0
tCPW
Clock Pulse Width
HIGH or LOW
COM
5
4
4
MIL
7
6
6
tPL
PC low
COM
6
5.5
5.5
MIL
8.5
8
8
tPLCPR
PC to CP recovery
COM
6
5
5
MIL
7.5
6.5
6.5
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-88
QUALITY SEMICONDUCTOR INC.
as
QSFCT193T, 2193T
Q
High-Speed CMOS
Presettable Synchronous
4-Bit Binary Counters
QS54/74FCT193T
QS54/74FCT2193T
FEATURES/BENEFITS
■ Pin and function compatible to the 74F193
74FCT193 and 74FCT193T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 193T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Standard and A speed grades with 6.5ns tPD for A
• lol = 64 mA Com., 48 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3 .5 V
Military product compliant to MIL-STD-883
FCT-T 2193T
• Built-in 25£2 series resistor outputs reduce
reflection and other system noise
Std and A speed grades with 6.5ns tPD for A
lol = 12mA Com.
DESCRIPTION
The QSFCT193 is a high speed CMOS 4-bit binary up/down counter. It has separate up and down clock
inputs, up/down ripple clock outputs and an asynchronous clear input. The '193 has asynchronous
preload inputs which override the count inputs. The '2193 is a 25Q resistor output version of the193,
and is useful for driving transmission lines and reducing system noise. All inputs have clamp diodes for
undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001).
FUNCTIONAL BLOCK DIAGRAM
CPU
Cup
Q+Cup
Cdn
-Cdn
<U
S
4
-► Q0-Q3
F3>
-►TCU
-► TCTJ
=
=======
QUALITY SEMICONDUCTOR INC.
4-89
QSFCT193T, 2193T
j
PIN CONFIGURATIONS
PDIP, SOIC
16 □ VCC
5 o ^ > 8
□ RC
H TC
-j
■
ALL PINS TOP VIEW
* For ZIP pinout contact factory
Of ; i..<
4-90
QUALITY SEMICONDUCTOR INC.
QSFCT193T, 2193T
=
PIN DESCRIPTION
■
Name
I/O
Description
DO-3
I
Data Inputs
QO-3
0
Data Outputs
PC
I
Pre Load
MR
I
Master Reset
CPU
I
Count Up Clock
CPD
I
Count Down Clock
TC~0
0
Terminal Count Up
TCD~
0
Terminal Count Down
FUNCTION TABLE
Inputs
Outputs
Function
it
PC
MR
CPU
CPD
Di
QO-3
TCU
TCD
X
H
X
X
X
0000
X
X
Reset
L
L
X
X
DO-3
DO-3
X
X
Load Data
H
L
T
H
X
Q+1
X
X
Count Up
H
L
H
t
X
Q-1
X
X
Count Down
H
L
L
H
X
F
L
H
Count Up = 1 1 1 1
H
L
H
H
X
0-E
H
H
Count Up * 1 1 1 1
H
L
H
L
X
0
H
L
Count Dn = 0000
H
L
H
H
X
1-F
H
H
Count Dn * 0000
QUALITY SEMICONDUCTOR INC.
4-91
QSFCT193T, 2193T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V(<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,4,5,9-11,14,15
4
4
5
7
PF
2,3,6,7,12,13
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
4-92
=
QUALITY SEMICONDUCTOR INC.
QSFCT193T, 2193T
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+5% Military TA = -55°C to 1 25° C, Vex: = 5.0V+1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
d)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
VII
inpui luw voitage
Logic LOW for All Inputs
n n
U.o
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
| lih|
|lil|
input ourrent
Input HIGH or LOW
Vcc = MAX
0 <. Vin < Vcc
D
U.A
lib
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
0
los
Short Circuit Current
FCTXXX
VCC = MAX,V0 = GND(2,3)
-60
-
-
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-U. /
-1 .£
Volts
Voh
OutDiit HIGH Voltanp
wui|jui nivjn v ullage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25£2)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
VCC = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol= 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vcq-5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-93
QSFCT193T, 2193T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
loc
Quiescent Power
Supply Current
Vcc -MAX, freq = 0
1.5
mA
0V£Vin<0.2V or Vcc-0.2V<Vin<Vcc
AlCC
Supply Current per
Input <§> TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-94
QUALITY SEMICONDUCTOR INC.
a
QSFCT193T, 2193T
======
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc =
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(1)
13
21
3
93
193A
2193A
Unit
Min
Max
Min
Max
Propagation Delay
CPU/DtoTCO/TCD
UUM
2.0
10
2.0
6.5
ns
tCPTC
MIL
2.0
10.5
2.0
6.9
tCPQ
Propagation Delay
CPU/DtoQi
COM
2.0
13.5
2.0
8.8
MIL
2.0
14.0
2.0
9.1
tDQ
Propagation Delay
Di to Qi
COM
2.0
15.5
2.0
10.1
MIL
1.5
16.5
2.0
10.8
tPLQ
Propagation Delay
PTtoQi
COM
2.0
14.0
2.0
8.8
MIL
2.0
13.5
2.0
9.1
tMRQ
Propagation Delay
MRtoQi
COM
3.0
15.5
3.0
10.1
MIL
3.0
16.0
3.0
10.4
tMRTCU
Propagation Delay
MRtoTCD
COM
3.0
14.5
3.0
9.4
MIL
3.0
15.0
3.0
9.8
Propagation Delay
MRtoTCD
COM
3.0
15.5
3.0
10.1
tMFrrco
MIL
3.0
16.0
3.0
10.4
Propagation Delay
PTtoTCD/D
COM
3.0
16.5
3.0
10.8
tPLTC
MIL
3.0
18.5
3.0
12.0
tDTC
Propagation Delay
DitoTCmS
COM
3.0
15.5
3.0
10.1
MIL
3.0
16.5
3.0
10.8
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-95
QSFCT193T, 2193T
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
193
193A
Unit
(1)
2193
2193A
Min
Max
Min
Max
tDPLS
Di to PC setup
COM
5.0
4.0
MIL
6.0
5.0
tDPLH
Di to PC hold
COM
2.0
1 .5
MIL
2.0
1.5
tPLW
PClowtime
COM
6.0
5.0
MIL
7.5
6.5
tCP
CPO/ETpulse width
high and low
COM
2
5.0
4.0
MIL
2
7.0
6.0
tCPL
CPU/B"pulse width low
(change of direction)
COM
2
10.0
8.0
MIL
2
12.0
10.0
tMRH
MR high time
COM
2
6.0
5.0
MIL
2
6.0
5.0
tRPLCP
PCVCPO/TTrecovery
COM
2
6.0
5.0
MIL
2
8.0
7.0
InMnt/r
MR"to"CPD/rjrecovery
COM
2
4.0
3.0
MIL
2
4.5
3.5
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
■
4-96
QUALITY SEMICONDUCTOR INC.
QSFCT240T, 241 T, 244T, 2240T, 2241 T, 2244T
=
Q
High Speed CMOS
8-Bit
Buffers/Line Drivers
QS54/74FCT240T
QS54/74FCT241T
QS54/74FCT244T
QS54/74FCT2240T
QS54/74FCT2241T
QS54/74FCT2244T
FEATURES/BENEFITS
• Pin and function compatible to the 74F240/1/4
74FCT 240/1/4 and 74FCT240T/1T/4T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 240T, 241 T, 244T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std., A, C, & D speed grades with 3.8 ns tPD for D
• to\ = 64 mA Com., 48 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2240T, 2241 T, 2244T
Built-in 25a series resistor outputs reduce
reflection and other system noise
Std., A, & C speed grades with 4.1 ns tPD for C
lol = 12mA Com
DESCRIPTION
The FCT240T, FCT241 T and FCT244T are 8-bit buffers/line drivers with three-state outputs that are
ideal for driving high-capacitance loads as in memory address and data buses. The FCT2240T,
FCT2241T and FCT2244T are 25£2 resistor output versions useful for driving transmission lines and
reducing system noise. The 2240, 2241 , 2244 series parts can replace the 240 series to reduce noise
in an existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs
have ground bounce suppression (see QSI Application Note AN-001), and outputs will not load an
active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
20" (19)
2A1(11)
2A2(13)
2A3(15) ^2^3(5)
2A4(17)f^o2Y4(3)
2Y1(9)
2Y2(7)
Note that pin 1 9 is 25 on the FCT244 and 2G for the FCT241
QUALITY SEMICONDUCTOR INC.
4-97
QSFCT240T, 241T, 244T, 2240T, 2241T, 2244T
PINOUTS
FCT240/241/244
FCT2240/2241/2244
PDIP, SOIC, QSOP
ZIP
1A1 C
2Y4C
1A2 C
2Y3 C
1A3 C
2Y2 C
1A4 C
2Y1 C 9
GNDC 10
1
20 □ VCC
19 □ 55/2G*
3 18 □ 1Y1 2Y3 (
17 □ 2A4
16 □ 1Y2
15 □ 2A3
14 □ 1Y3
13 □ 2A2
12 P 1Y4
11
□ 2A1
ALL PINS TOP VIEW
*Note: Pin 19 is 25 for the 240/244 and is 2G for the 241
FUNCTION TABLES
FCT240/FCT2240
T5/25
Input A
Output Y
H
X
Z
L
L
H
L
H
L
FCT244/FCT2244
TG/2G
Input A
Output Y
H
X
Z
L
L
L
L
H
H
FCT241/FCT2241
m
2G
Input A
Output Y
H
H
X
Z
L
L
L
L
L
L
H
H
H-High. L-Low, Z-High Impedance
4-98
QUALITY SEMICONDUCTOR INC.
QSFCT240T, 241T, 244T, 2240T, 2241T, 2244T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V|
-0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature -65°to+165°C
■
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
1,19
2-9,11-18
SOIC
QSOP
Note: Capacitance is characterized but not tested
PDIP.LCC
ZIP
10 pF
Unit
PF
PF
■
QUALITY SEMICONDUCTOR INC.
4-99
QSFCT240T, 241T, 244T, 2240T, 2241T, 2244T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
_
_
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
0.2
l«h|
|l|
Input Current
Input HIGH or LOW
Vcc=MAX
0 < Vin < Vcc
_
_
5
uA
|k>z|
Off State Output
Current (Hi-Z)
Vcc=MAX,0<;Vin<Vcc
_
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX (25Q)
Vcc = Min,Vo=2.0V
50
mA
Vic
Input Clamp Voltage
Vcc=MIN, lin = 18mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and T/^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-100
QUALITY SEMICONDUCTOR INC.
QSFCT240T, 241 T, 244T, 2240T, 2241 T, 2244T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. PerTTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Iccan be computed using the above parameters as explained in the Technical Overview section.
-
QUALITY
4-101
QSFCT240T, 241T, 244T, 2240T, 2241T, 2244T
=
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
FCT240, FCT2240
Symbol
Description
Notes
240,
240A,
240C,
240D
Unit
I1 )
2240
2240A
2240C
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to Yi, FCT240
Com
1.5
8
1.5
4.8
1.5
4.1
1.5
3.8
ns
MM
1.5
9
1.5
5.1
Propagation Delay
AitoYi, FCT2240
Com
1.5
8
1.5
4.8
1.5
4.1
Mil
1.5
9
1.5
5.1
tPZH
tPZL
Output Enable Time
OEtoYi,FCT240
Com
1.5
10
1.5
6.2
1.5
5.8
1.5
5.6
MM
1.5
10.5
1.5
6.5
Output Enable Time
OEtoYi, FCT2240
Com
1.5
10
1.5
6.2
1.5
5.8
MM
1.5
10.5
1.5
6.5
tPHZ
tPLZ
Output Disable Time
OEtoYi
Com
2
1.5
9.5
1.5
5.6
1.5
5.2
1.5
5.2
MM
2
1.5
10.0
1.5
5.9
FCT241, FCT244, FCT2241, FCT2244
Symbol
Description
Notes
(1)
241/4,
2241/4
241/4 A,
2241/4A
241/4C,
2241/4C
244D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
AitoYi,FCT241/4
COM
1.5
6.5
1.5
4.8
1.5
4.1
1.5
3.8
ns
MIL
1.5
7.5
1.5
5.1
Propagation Delay
AitoYi, FCT2241/4
COM
1.5
6.5
1.5
4.8
MIL
1.5
7.5
1.5
5.1
tPZH
tPZL
Output Enable Time
OEtoYi, FCT241/4
COM
1.5
8
1.5
6.2
1.5
5.8
1.5
5.6
MIL
1.5
8.5
1.5
6.5
Output Enable Time
OEtoYi, FCT2241/4
COM
1.5
8
1.5
6.2
MIL
1.5
8.5
1.5
6.5
tPHZ
tPLZ
Output Disable Time
OEtoYi
COM
2
1.5
7
1.5
5.6
1.5
5.2
1.5
5.2
MIL
2
1.5
7.5
1.5
5.9
Notes:
1. Minimum propagation delay values are guaranteed but not tested.
2. This parameter is guaranteed but not tested.
4-102
QUALITY SEMICONDUCTOR INC.
QSFCT245T, 640T, 2245T, 2640T
Q
High Speed CMOS
8-Bit Transceivers
QS54/74FCT245T
QS54/74FCT640T
QS54/74FCT2245T
QS54/74FCT2640T
FEATURES/BENEFITS
=
=
Pin and function compatible to the 74F245/640
74FCT245/640 and 74FCT245T/640T
CMOS power levels: <7.5 mW static
Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 245T, 640T
JEDEC-FCT spec compatible
Fastest CMOS logic family available
Std., A, C, and Dspeed grades; 3.8 ns tPD for D
lol = 64 mA Com., 48 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3 .5 V
Military product compliant to MIL-STD-883
FCT-T 2245T, 2640T
■ Built-in 2SQ series resistor outputs reduce
reflection and other system noise
• Std., A, and C speed grades; 4.1 ns tPD for C
' lol = 12mA Com.
=
DESCRIPTION
The QSFCT245AT/CT and QS FCT2245 AT/CT are 8-bit non-inverting transceiversthat have three-state
outputs which are useful for bus-oriented applications. The Transmit/Receive (T/R) input determines the
direction of data flow, either from A to B or B to A, and the Output Enable (UE) input enables the selected
port for output. The FCT2245AT/CT and FCT2640AT/CT are 25a resistor output versions useful for
driving transmission lines and reducing system noise. The 2245 parts can replace the 245 series to
reduce noise in an existing design. All inputs have clamp diode for undershoot noise suppression. All
outputs have ground bounce suppression (see QSI Application Note AN-001), and outputs will not load
an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
25Q,FCT2xxx only
25Q,FCT2xxx only
1 Inverting Drivers on 640/2640 Only
(245/2245 have Non-Inverting Drivers)
QSFCT245T, 640T, 2245T, 2640T
PINOUTS
PDIP, SOIC, QSOP
ZIP
t/rC
AO C
A1 C
A2C
A3 C 5 16 □ B2
A4 C
A5 C
A6 C
A7C
gndC 10
20 □ VCC
□ ot
□ BO
□ B1
19
18
17
15
14
13
12
11
□ B3
□ B4
□ B5
□ B6
□ B7
ALL PINS
T/R ( 1<
A1 ( 3
A3 ( 5
A5(
A7(
B7(
B5 (
B3 (
B1 ( 17
19
4
6
8
10
12
14
16
18
VIEW
2 ) AO
) A2
) A4
) A6
) GND
) B6
) B4
) B2
) BO
20 ) VCC
INDEX
-
PIN DESCRIPTION
FUNCTION TABLE
Name
I/O
Description
0"E
A
B
Function
Ai
I/O
Data Bus A
H
X
Hi-Z
Hi-Z
Disable
Bi
I/O
Data Bus B
L
L
Output
Input
Bus B to Bus A
T/R
I
Direction
L
H
Input
Output
Bus A to Bus B
0~E"
I
Output Enable
H=High, L=Low, Hi-Z-High Impedance
4-104
QUALITY SEMICONDUCTOR INC.
QSFCT245T, 640T, 2245T, 2640T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V, -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V(<0 -20 mA
DC Output Diode Current with V0 <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Numberof Outputs, M=Numberof inputs
Maximum Power Dissipation 0.5 watts
TSTGStoraQe Temperature -65° to +165°C
CAPACITANCE
TA = 25°C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,19
4
4
5
7
pF
6
6
7
9
PF
2-9,11-18
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY SEMICONDUCTOR INC.
4-105
QSFCT245T, 640T, 2245T, 2640T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=50V±5% Military TA=-55°C to 1 25°C, Vcc=5 0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
Max
Unit
vin
Input High Voltage
Logic HIGH for All Inputs
\lr\\\c
VOIIS
VI I
input luw voltage
Logic LOW for All Inputs
U.o
AVI
Input Hysterisis
Vtlh-Vthl for All Inputs
U .c.
|ih|
I i:i I
|H|
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
-
c
uA
|bz|
Off State Output
Current (Hi-2)
Vcc = MAX, 0< Vin < Vcc
-
-
5
tos
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
_ ,
mA
lor
Current Drive
FCT2XXX (2K1)
Vcc = Min, Vo =2.0V
50
-
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-0.7
Volts
-
-1.2
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
VCC = MIN
lol = 12 mA (MIL)
21
28
38
Q.
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vcc=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
=
4-106
QUALITY SEMICONDUCTOR INC.
QSFCT245T, 640T, 2245T, 2640T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial: Ta = 0 °C to 70 °C, Vcc = 5.0V ±5% Military: Ta = -55 °C to +1 25 °C, Vcc = 5.0V ±1 0%
Cload = 50 pF, Rload = 500Q unlesss otherwise noted.
Symbol
Description
Notes
(D
245,
640,
2245,
2640
245A,
640A,
2245A,
2640A
245C,
2245C
245D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to/from Bi, 245,640
COM
1.5
7
1.5
4.6
1.5
4.1
1.5
3.8
ns
MIL
1.5
7.5
1.5
4.9
Propagation Delay
Ai to/from Bi, 2245,2640
COM
1.5
7
1.5
4.6
1.5
4.1
MIL
1.5
7.5
1.5
4.9
tPZH
tPZL
Output Enable Time
OE, T/R to A/B, 245,640
COM
1.5
9.5
1.5
6.2
1.5
5.8
1.5
5.6
MIL
1.5
10
1.5
6.5
Output Enable Time
OE,T/Rto A/B, 2245,2640
COM
1.5
9.5
1.5
6.2
1.5
5.8
MIL
1.5
10
1.5
6.5
tPHZ
tPLZ
Output Disable Time
OE, T/R to A/B
COM
2
1.5
7.5
1.5
5
1.5
4.5
1.5
4.5
MIL
2
1.5
10
1.5
6
Notes:
1. Minimum propagation delay values are guaranteed but not tested.
2. This parameter is guaranteed but not tested.
QUALITY SEMICONDUCTOR INC. 4-107
QSFCT245T, 640T, 2245T, 2640T
Nl
4-108
QUALITY SEMICONDUCTOR INC.
QS273T, 2273T
High-Speed CMOS
8-Bit Register with
Asynchronous Reset
QS54/74FCT273T
QS54/74FCT2273T
FEATURES/BENEFITS
• Pin and function compatible to the 74F273
74FCT 273 and 74FCT273T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 273T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A and C speed grades with 5.2ns tPD for C
• lol = 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2273T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• Std, A and C speed grades with 5.2ns tPD for C
• lol = 12mA Com.
DESCRIPTION
The QSFCT273T and QSFCT2273T are high speed CMOS TTL-compatible registers with an
asynchronous reset input. They are eight -bit registers with a buffered common clock and a buffered
output drive. The QSFCT2273T is a 25Q resistor output version useful for driving transmission lines
and reducing system noise. Data is stored in the register on the rising edge of the clock. The high
output current lol and loh drive high capacitance loads. All inputs have clamp diodes for undershoot
noise suppression. All outputs have ground bounce suppression (see QSI Application Note AN-001),
and outputs will not load an active bus when Vcc is removed from the device.
NCTIONAL BLOCK DIAGRAM
FCT273
CLEAR CLR
QUALITY SEMICONDUCTOR INC.
4-109
QS273T, 2273T
PIN CONFIGURATIONS
FCT273, 2273
PDIP, SOIC, QSOP
ZIP
CM
"l8C
5 07
17C
L D6
16C
L 06
15C
L 05
CO
ALL PINS TOP VIEW
PIN DESCRIPTION AND FUNCTION TABLE
FCT273, 2273
Name
I/O
Description
Di
i
Data Inputs
Oi
0
Data Outputs
CP
I
Clock Input
era
I
Clear Input
Inputs
CUE
H
H
CP
Di
Internal
Q
Value
H
Outputs
Oi
H
Function
Clear Register
Load Input Data
4-110
QUALITY SEMICONDUCTOR INC.
QS273T, 2273T
=
Itage to Ground ,
-0.5Vto+7.0V
.. Voltage VQ -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGStorage Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,3,4,7,8,11,13,14,17,18
4
4
5
7
PF
2,5,6,9,12,15,16,19
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY SEMICONDUCTOR INC.
4-111
QS273T, 2273T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C. VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(D
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
\m\
mi
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
uA
|toz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
-
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
£1
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-112
QUALITY SEMICONDUCTOR INC.
QS273T, 2273T
3
POWER SUPPLY CHARACTERISTICS
■
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
ICC
Quiescent Power
wt wlwwWwl 11 1 w¥» wl
Supply Current
Vcc = MAX frea = 0
v ww ^ l¥l*W*| itwWJ ~ w
0V<Vin<0.2V or Vcc-0.2V^Vin<Vcc
1 .5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
' '
0.25
mA/
MHz
'
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC £
2. Per TTL driven input (Vi-3.4V)
3. For flipfbps Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as i
QUALITY SEMICONDUCTi
4-113
QS273T, 2273T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+5% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbt
(1
'7
• J
Description
riOlBS
(■ )
273,
2273
273A,
2273A
273C,
2273C
Unit
Min
Max
Min
Max
Min
Max
tPHL
tPLH
F
C
ropagation Delay
IP, CLRtoOi, 273
Com
2
13
2
7.2
2
5.2
ns
Mil
15
2
8.3
2
Propagation Delay
CP, CLRtoOi, 2273
Com
2
13
2
7.2
2
5.2
MM
2
15
2
8.3
ts
3
2
1.5
Data Setup Time
Dito CP
Com
MM
3.5
2
tH
Data Hold Time
Dito CP
Com
2
1.5
1
Mil
2
1.5
tWCP
Clock Pulse Width
HIGH or LOW
Com
2
7
6
4
Mil
7
6
tWCLR
CLR Pulse Width
HIGH or LOW
Com
2
7
6
5
Mil
7
6
tREC
CLR Recovery Time
CLR to CP
Com
2
4
2
1.5
Mil
5
2.5
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-114
QUALITY SEMICONDUCTOR INC.
—
QS280T, 1280T
Q
High Speed CMOS
9-Bit Parity
Generator/Checker
QS54/74FCT280T
QS54/74FCT1280T
FEATURES/BENEFITS
QSFCT280BT faster than FAST™ • 6.3 ns delay, I x to Se for QSFCT280BT
QSFCT1 280T has 18 enable, registered outputs • 2 ns setup, Ix to reg clock for QSFCT128i
lol=48 mA COM, 32 mA MIL • CMOS power levels < 7.5 mW static
TTL-compatible input and output levels • Available in PDIP, ZIP, SOIC, CERDIP,
Military product compliant with MIL-STD 883 • JEDEC standard pinouts
==
DESCRIPTION
The QSFCT280/AT/BT and QSFCT1 280/AT/BT are high speed CMOS TTL-compatible 9-bit parity
generator-checkers. Both odd and even parity outputs are available for generating or checking odd or
even parity. The 1 280 has 18 enable for parity bit generation and registered odd and even outputs for
parity check on the following cycle. All inputs have clamp diodes for undershoot noise suppression. All
outputs have ground bounce suppression (see QSI Application Note AN-001).
QUALITY SEMICONDUCTOR INC.
4-115
QS280T, 1280T
FCT280 PIN CONFIGURATIONS
PDIP, SOIC, QSOP
ZIP
GND C 7
*
<
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
)I8
o Q O o
W § *
PIN DESCRIPTION FUNCTION TABLE
Pin Name
I/O
Description
Inputs
Outputs
Function
I0-I8
I
Data In
I0-I8
Z even
Zodd
I even
0
Even Parity Out
Number of Bits
H
L
Parity is Even
I odd
0
Odd Parity Out
at TTL High
= 0,2,4,6,8
Number of Bits
at TTL High
= 1,3,5,7,9
L
H
Parity is Odd
4-116 QUALITY SEMICONDUCTOR INC.
QS280T, 1280T
FCT1280 PIN CONFIGURATIONS
PDIP, SOIC, QSOP
ZIP
ISC
leC
I7C
EN8 C
»C
leC
QleC
GND C
8
9
10
'20
19
18
17
16
15
14
13
12
11 □
□ vcc
□ m
□ 13
□ 12
□ M
□ 10
□ CLK
□ CEN
□ OER
CTR
ALL PINS TOP VIEW
PIN DESCRIPTION
Name
I/O
Description
I0-I8
Data In
EN8
Enable 18
CLK
Clock
CER
Clock Enable
CCR
Clear
OER
Reg Out Enable
le
0
Even Parity Out
So
o
Odd Parity Out
Qle
o
Reg even Parity
QSo
0
Reg odd Parity
INDEX
EN8 T
1 4
18 II
1 5
Ee T
1 6
lo T
] 7
QSeT
1 8
FUNCTION TABLE
Inputs
Outputs
10-17
18
EN8
le
So
Number of Bits
at TTL High
= 0,2,4,6,8
X
L
H
L
L
H
H
L
H
H
L
H
Number of Bits
at TTL High
= 1,3,5,7
X
L
L
H
L
H
L
H
H
H
H
L
Inputs
Outputs
Function
OER
CEN
CLR
CLK
Qle
QIo
H
X
X
X
Hi-Z
Hi-Z
Disable
L
X
L
X
L
L
Clear
L
H
H
T
QIon-1
QSon-1
No Change
L
L
H
T
Ien-1
Ion-1
Loadle, lo
TOR INC.
4-117
QS280T, 1280T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq. <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature -65° to +165°C
4-118
QUALITY SEMICONDUCTOR INC.
QS280T, 1280T
CAPACITANCE
FCT280
TA = 25°C, f=1 MHz,Vin = OV,Vout = OV
-
Pins
1,2,4,8-13
5,6
SOIC
QSOP
PDIP.LCC
ZIP
8 | 8 | 9 | 10
is characterized but not tested
Unit
PF
PF
PF
FCT1280
TA = 25°C, f=1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-5,11-19
4
4
5
7
PF
6-9
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
-
QUALITY SEMICONDUCTC
4-119
QS280T, 1280T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 125°C, VCC=5.0V±10%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
0.2
I ■« I
( 1:1 1
|lll|
Input Current
Inm i4 LI 1 ^ LI «M 1 /"\\A/
Input HICjH or LOW
Vcc = MAX
0 < Vin < Vcc
-
5
uA
\m
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc =MIN,lin = 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FPTYYY Z FPT9YYY
1 L» 1 AAA a IV 1 fcAAA
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
-
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25£2)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-120 QUALITY SEMICONDUCTOR INC.
QS280T, 1280T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
uv<vin<u.2v or vcc-o.2v<vin<vcc
1.5
mA
AlcC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mN
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
dr ve load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
■
4-121
QS280T, 1280T
— — ^ — — -— ^— — —
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
I 1
Description
Notes
(1)
280T
1280T
280AT
1280AT
280BT
1280BT
Unit
Min
Max
Min
Max
Min
Max
tPHLE
tPLHE
Propagation Delay
10 - 18 to leven
Com
10
7.5
6.3
ns
Mil
11
9
tPHLO
t PLHO
Propagation Delay
10 - 18 to lodd
Com
10
7.5
6.3
Mil
11
9
1280 Only
tOE
Output Enable Time
ROEtoQZe.QXo
Com
1.5
12.5
1.5
7.5
ns
Mil
1.5
14
1.5
toz
Output Disable Time
ROE Qle, QIo
Com
2
1.5
8
1.5
6.5
Mil
2
1.5
8
1.5
tCPQ
Clock to Output
QZe, QZo
Com
10
9
7.5
Mil
11
10
tCLR
CLR to Output
Q£e, QIo
Com
13
11
8
Mil
15
13
tcs
CEN Setup Time
CEN to CLK
Com
2.5
2
2
Mil
tCH
CEN Hold Time
CEN to CLK
Com
3
2.5
2
Mil
ts
Data Setup Time
Ix to CLK
Com
2.5
2
2
Mil
tH
Data Hold Time
Ix to CLK
Com
3
2.5
2
Mil
tw
Clock Pulse Width
High or Low
Com
2
7
7
5
Mil
2
7
7
6
1 . See test circuits and wave forms.
2. This parameter guaranteed by design but not tested.
4-122 QUALITY SEMICONDUCTOR INC.
QS299T, 2299T
Q
High-Speed CMOS
8-bit Universal
Shift Register
QS54/74FCT299T
QS54/74FCT2299T
-
FEATURES/BENEFITS
• Pin and function compatible to the 74F299
74FCT 299 and 74FCT299T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 299T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Standard and A speed grades with 9.5ns tPD for A
• lol= 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
DESCRIPTION
=
FCT-T 2299T
• Built-in 25i2 series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 9.5ns tPD for A
• lol = 12mA Com.
The QSFCT299T and QSFCT2299T are high speed CMOS 8-bit universal shft registers. The contents
of the 8-bit register may be loaded from a bus, shifted left or right, or gated to the bus. The 2191 is a
25£2 resistor output version of the 299, and is useful for driving transmission lines and reducing system
noise. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground
bounce suppression (see QSI Application Note AN-001).
FUNCTIONAL BLOCK DIAGRAM
DS7
DSO
S1
SO
CP
MR
OE1
OE2
\1 \f
£3
L3.
S=3
Load
S=2
Right
S-1
Left
S=0
Hold
Multiplexer
C w
E
8-bit Register
Q1-Q6
Q0|
il — U 1
FCT2xxx only
G
£ FCT2xxx only
' I/O0-7
QUALITY
4-123
QS299T,
PIN CONFIGURATIONS
PDIP, SOIC, QSOP
° °- n
CO O O
1/05
1/03
ALL PINS TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE
Name
I/O
Description
I/O0-7
I/O
Data I/O Bus
S0.S1
1
Function Select
CP
1
Clock
Q0.Q7
0
Shift Out
DS0.DS1
1
Shift In
DET.TJE5
1
Output Enables
MR
Master Reset
Inputs
Outputs
Function
MR
S1
SO
CP
Q7
Q6-1
QO
L
X
X
X
L
LLLLLL
L
Reset
H
L
L
t
Q7
Q6-1
QO
Hold Data
H
L
H
t
DS7
Q7-2
Q1
Shift Left
H
H
L
T
Q6
Q5-0
DSO
Shift Right
H
H
H
I/07
1/06-1
l/OO
Load
—
4-124
QUALITY SEMICONDUCTOR INC.
2299T
ABSOLUTE
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width ^20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
CAPACITANCE
assess
I ,
3
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-3,9,11,12,18,19
4
4
5
7
PF
8,17
6
6
7
9
PF
4-7,13-16
8
8
9
10
PF
Note: Capacitance is characterized but not tested
-
QUALITY SEMICONDUCTOR INC.
sssssssss
4-125
QS299T, 2299T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
-
| Ml ]
Mill
Input Current
Input HIGH or LOW
Vcc=MAX
0 < Vin < Vcc
-
-
5
uA
Itazl
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
FCTXXX
lor
Current Drive
Vcc = Min, Vo =2.0V
50
-
-
mA
FCT2XXX
Vic
Input Clamp Voltage
Vcc = MIN,lin= 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FPTYYY Z FPT9YYY
IV 1 AAA Ol l\s 1 i-AAA
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
-
Volts
loh= 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (2512)
Vcc = MIN
bl = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
bl = 12 mA (MIL)
21
28
38
lol= 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vq^=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-126
QUALITY SEMICONDUCTOR INC.
QS299T, 2299T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
Alec
Supply Current per
Input @TTL HIGH
Vcc=MAX,Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMU
4-127
QS299T, 2299T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V+5% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
299
2299
299A
2299A
Unit
Min
Max
Min
Max
tCPQ
Propagation Delay
CPtoQi
COM
2
10
2
7.2
ns
MIL
2
14
2
9.5
tCPI
Propagation Delay
COM
2
12
2
7.2
CP to I/O
MIL
2
12
2
9.5
tMRQ
Propagation Delay
MR to Qi
COM
2
10
2
7.2
MIL
2
10.5
2
9.5
tMRI
P7&toi/o y
COM
2
15
2
8.7
MIL
2
15
2
11.5
tPZH/L
Output Enable Time
OE tp I/O
-*
COM
1.5
11
1.5
6.5
MIL
1.5
15
1.5
7.5
tPHZ.LZ
Output Disable Time
OE to I/O
COM
1.5
7
1.5
5.5
MIL
1.5
9
1.5
6.5
tS4
Setup Time
SO, SI to CP
COM
7.5
3.5
MIL
7.5
4.0
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-128 QUALITY SEMICONDUCTOR INC.
QS373T, 533T, 2373T, 2533T
Q
High-Speed CMOS
Bus Interface
8-Bit Latches
QS54/74FCT373T
QS54/74FCT533T
QS54/74FCT2373T
QS54/74FCT2533T
FEATURES/BENEFITS
• Pin and function compatible to the 74F373/533
74FCT373/533 and 74FCT373T/533T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 373T, 533T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std. , A , C, and D speed grades with 4.2ns for D
• lol = 48 mA Com., 32 mA Mil.
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3 ,5V
• M ilitary product compliant to M IL-STD-883
FCT-T 2373T, 2533T
• Built-in 25i2 series resistor outputs reduce
reflection and other system noise
• Std. , A , C, & D speed grades with 4.2ns for D
• lol = 12mA Com.
DESCRIPTION
The QSFCT373T and QSFCT533T are 8-bit high-speed CMOS TTL-compatible buffered latches with
three-state outputs that are ideal for driving high capacitance loads such as memory and address buses.
The 2373/533 devices are 25Q resistor output versions useful for driving transmission lines and
reducing system noise. The 2373 and 2533 series parts can replace the 373 series to reduce noise in
existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs have
Ian;
und bounce suppression (see QSI Application Note AN-001), and outputs will not toad i
in Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
FCT373
-Oi
>—
25Q
FCT533
FCT2xxx only
QUALITY SEMICONDUCTOR INC.
4-129
QS373T, 533T, 2373T, 2533T
PINOUTS
PDIP, SOIC, QSOP
ZIP
0E<
D0(
OK
D2(
03 (
LE(
D4(
05 ( 15
D6 ( 17
07( 19
3
5
7
9
11
13
2 ) OO
4 ) D1
6 )02
D3
) GND
) CM
) D5
) 06
) D7
INDEX
ALL PINS TOP VIEW
20 1) VCC
PIN DESCRIPTION AND FUNCTION TABLE
FCT373, 2373
Name
I/O
Description
Df
I
Data Inputs
Oi
0
Data Outputs
LE
I/O
Latch Enable
OE
I/O
Output Enable
Inputs
Internal
Q
Value
Outputs
Function
0"E
LE
Di
373
533
Oi
01
H
X
X
X
Z
z
Disable Outputs
L
X
X
H
H
L
Enable Outputs
L
X
X
L
L
H
X
H
L
L
X
X
Pass Input Data
X
H
H
H
X
X
X
L
X
Q
X
X
Hold Prior Data
4-130
QUALITY SEMICONDUCTOR INC.
QS373T, 533T, 2373T, 2533T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation. • • • .....U.O WaTlS
TSTGstora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz
Pins
1,3,4,7,8,11,13,14,17,18
2,5,6,9,12,15,16,19
—
SOIC
8
QS0P
PDIP.LCC
Note: Capacitance is characterized but not tested
ZIP
10
Unit
PF
PF
PF
QUALITY SEMICONDUCTOR INC.
4-131
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
-
0.2
|lih|
Mill
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
uA
|ka|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX,Vo = GND(2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
Volts
loh = 15 mA (COM)
2.4
-
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
IOl = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25ft)
Vcc = MIN
lol= 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25ft)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
a
lol= 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vcc=5-0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-132
QUALITY SEMICONDUCTOR INC.
QS373T, 533T,
POWER SUPPLY
STICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
1.5
mA
0V<Vin<0.2V or Vcc-0.2V<MnsVcc
A.CC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
0.25
mA/
MHz
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
4,
For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
Per TTL driven input (Vi-3.4V)
For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
Ic can be computed using the above parameters as explained in the Technical Overview section.
■
QUALITY SEMICONDUCTOR INC.
4-133
QS373T, 533T, 2373T, 2533T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(D
373
2373
533
2533
373A
2373A
533A
2533A
373C,
2373C
533C
2533C
373D
2373D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Data to Oi, 373
COM
1.5
8
1.5
5.2
1.5
4.7
1.5
4.2
ns
MIL
2
8.5
1.5
5.6
Propagation Delay
Data to Oi, 2373
COM
1.5
8
1.5
5.2
1.5
4.7
1.5
4.2
MIL
2
8.5
1.5
5.6
tPHLE
tPLHE
Propagation Delay
LE high to Oi, 373
COM
2
13
2
8.5
2
6.9
1.5
6.3
MIL
2
14
2
9.8
Propagation Delay
LE high to Oi, 2373
COM
2
13
2
8.5
2
6.9
1.5
6.3
MIL
2
14
2
9.8
tPZH
tPZL
Output Enable Time
CEtoYi, 373
COM
1.5
11
1.5
6.5
1.5
5.5
1.5
5.5
MIL
1.5
12.5
1.5
7.5
Output Enable Time
CE to Yi, 2373
COM
1.5
11
1.5
6.5
1.5
6.2
1.5
6.2
MIL
1.5
12.5
1.5
7.5
tPHZ
tPLZ
Output Disable Time
OEtoYi
COM
2
1.5
7
1.5
5.5
1.5
5.0
1.5 I 5.0
MIL
2
1.5
8.5
1.5
6.5
ts
Data Setup Time
DitoLE hi to low
COM
2
2
2
2
MIL
2
2
tH
Data Hold Time
DitoLE hi to tow
COM
1.5
1.5
1.5
1.5
MIL
1.5
1.5
tw
LE Pulse Width
HIGH or LOW
COM
2
6
5
4
4
MIL
2
6
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
QS374T, 534T, 2374T, 2534T
Q
High-Speed CMOS
Bus Interface
8-Bit Registers
i
QS54/74FCT374T
QS54/74FCT534T
QS54/74FCT2374T
QS54/74FCT2534T
—
FEATURES/BENEFITS
=
—
—
• Pin and function compatible to the 74F374/534
74FCT374/534and 74FCT374T/534T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 374T, 534T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A ,C, & D speed grades with 4.5 ns tPD for D
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2374T, 2534T
• Built-in 25Q. series resistor outputs reduce
reflection and other system noise
• Std, A and C speed grades with 5.2 ns tPD for C
• lol = 12mA Com.
DESCRIPTION
The QSFCT374T and QSFCT534T are high speed CMOS TTL-compatible buffered registers. They are
eight-bit registers with a buffered common clock and a buffered output enable control. The
QSFCT2374T and QSFCT2534T are 25fl resistor output versions useful for driving transmission lines
and reducing system noise. Data is stored in the register on the rising edge of the clock. The FCT374
is a non-inverting device, and the FCT534 is an inverting device. The high output current lol and loh
drive high capacitance loads. All inputs have clamp diodes for undershoot noise suppression. All
outputs have ground bounce suppression (see QSI Application Note AN-001), and outputs will not
load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
FCT374
DATADi -
FCT53*
CLOCK CP — >CP
OUTPUT ENABLE EE
OUTPUT ENABLED
FCT2xxx only
QUALITY SEMICONDUCTOR INC.
4-135
QS374T, 534T, 2374T, 2534T
PIN CONFIGURATIONS
FCT374, 534, 2374, 2534
PDIP, SOIC, QSOP
ZIP
ALL PINS TOP VIEW
PIN DESCRIPTION AND FUNCTION TABLE
FCT374, 534, 2374, 2534
Name
I/O
Description
Inputs
Internal
Outputs
Function
Di
1
Data Inputs
0~E
CP
Di
Q
Value
374
534
Oi
0
Data Outputs
Oi
01
CP
1
Clock Input
H
X
X
X
z
Z
Disable Outputs
0~E
1
Output Enable
L
T
L
L
L
H
Load Input Data,
L
T
H
H
H
L
Enable Output
H
T
L
L
Z
Z
Load Input Data,
H
T
H
H
z
Z
Disable Output
4-136
QUALITY SEMICONDUCTOR INC.
QS374T, 534T, 2374T, 2534T
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with V0 <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TsTfiStorage Temperature -65° to +1 65°C
CAPACITANCE
TA = 25°C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
1,3,4,7,8,11,13,14,17,18
2,5,6,9,12,15,16,19
SOIC
8
QSOP
PDIP.LCC
ZIP
10 pF
Unit
PF
PF
Note:
Capacitance is characterized but not tested
-
QUALITY SEMICONDUCTOR INC.
4-137
QS374T, 534T, 2374T, 2534T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, Vcc=5-0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
■ ' *
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
-
| lih|
i in i
Input Current
Inrutt WII^M rtr I OW
inpui nion or luw
Vcc= MAX
0 < Vin < Vcc
-
-
5
uA
Off State Output
ourrent (ni-^j
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
FCTXXX
lor
Current Drive
Vcc = Min, Vo =2.0V
50
-
-
mA
FCT2XXX
Vic
Input Clamp Voltage
Vcc=MIN, lin = 18mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lot = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
a
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate VCC=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-138
QS374T, 534T, 2374T, 2534T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
loc
Quiescent Power
Supply Current
Vcc=MAX, freq = 0
0V^Vin^0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @ TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes e
clock cycle. This is a measurement of device power consumption only and does not include power t
drive load capacitance or tester capacitance. This parameter is guaranteed by (
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
j
-
:
—
4-139
QS374T, 534T, 2374T, 2534T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
374
534
2374
2534
374A
534A
2374A
2534A
374C
534C
2374C
2534C
374D
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
CP to Oi, 374/534
COM
2
10
2
6.5
2
5.2
1.5
4.5
MIL
2
11
2
7.2
Propagation Delay
CP to Oi. 2374/2534
COM
2
10
2
6.5
2
5.2
MIL
2
11
2
7.2
tPZH
tPZL
Output Enable Time
OEtoYi, 374/534
COM
1.5
12.5
1.5
6.5
1.5
5.5
1 .5
5.5
MIL
1.5
14
1.5
7.5
Output Enable Time
OEtoYi, 2374/2534
COM
1.5
12.5
1.5
6.5
1.5
6.2
MIL
1.5
14
1.5
7.5
tPHZ
tPLZ
Output Disable Time
OEtoYi
COM
2
1.5
8
1.5
5.5
1.5
5
1.5
5
MIL
2
1.5
8
1.5
6.5
ts
Data Setup Time
DitoCP
COM
2
2
1.5
1.5
MIL
2
2
tH
Data Hold Time
DitoCP
COM
1.5
1.5
1
1
MIL
1.5
1.5
tw
Clock Pulse Width
HIGH or LOW
COM
2
7
5
4
4
MIL
2
7
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-140
^ ■
QUALITY SEMICONDUCTOR INC.
QS377T, 2377T
Q
High-Speed CMOS
8-Bit Register with
Clock Enable
QS54/74FCT377T
QS54/74FCT2377T
FEATURES/BENEFITS
• Pin and function compatible to the 74F377
74FCT377 and 74FCT377T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 377T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A and C speed grades with 5.2ns tPD for C
• lol = 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 2377T
• Built-in 25C1 series resistor outputs reduce
reflection and other system noise
• Std., A & C speed grades with 5.2ns tPD for C
• lol = 12mA Com.
=
DESCRIPTION
The QSFCT377T and QSFCT2377T are high speed CMOS TTL-compatible registers. They are eight -
bit registers with a buffered common clock, a buffered output drive and a synchronous clock enable.
The QSFCT2377T is a 25£2 resistor output version useful for driving transmission lines and reducing
system noise. Data is stored in the register on the rising edge of the clock if the clock enable input is
active. The high output current lol and loh drive high capacitance loads. All inputs have clamp diodes
for undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001), and outputs will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
QUALITY SEMICONDUCTOR INC.
4-141
QS377T, 2377T
PIN CONFIGURATIONS
FCT377, 2377
PDIP, SOIC, QSOP
ZIP
ALL PINS TOP VIEW
PIN DESCRIPTION AND FUNCTION TABLE
FCT377, 2377
Name
I/O
Description
Di
1
Data Inputs
Oi
0
Data Outputs
CP
1
Clock Input
CE
1
Clock Enable
Inputs
Internal
Q
Value
Outputs
1 1
Function
CE
CP
Di
Oi
H
X
X
NC
L
Hold Value
L
T
L
L
L
Load Input Data
L
T
H
H
H
!
4-142
QUALITY SEMICONDUCTOR INC.
QS377T, 2377T
=
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground
DC Output Voltage Vq
-0.5V to 7.0V
-0.5V to 7.0V
-3.0V
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
I
TSTGStoraae Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,3,4,7,8,11,13,14,17,18
4
4
5
7
PF
2,5,6,9,12,15,16,19
6
6
7
9
PF
8
8
9
10
1 1
PF
1 1
-
■
■
QUALITY SEMICONDUCTOR INC.
4-143
QS377T, 2377T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
VII
input luh voiidge
Logic LOW for All Inputs
n r
AVt
ii V l
Inruit Wvcforicic
Vtlh-Vthl for All Inputs
0 2
I* I
in
Input Current
Input HIGH or LOW
Vcc=MAX
0 < Vin < Vcc
-
-
5
uA
|bz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
_
_
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
_
_
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
loU 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (2K2)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (2K2)
VCC = MIN
lol = 12 mA (MIL)
21
28
38
CI
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
-
4-144 QUALITY SEMICONDUCTOR INC.
QS377T, 2377T
POWER SUPPLY C
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
ICC
uuiesceni rowBi
Supply Current
_ MAY Iran _ ft
VCC = MAA, TlcCf = U
0V<Vin<;0.2V or Vcc-0.2V<Vin<Vcc
1 .0
mA
AlOC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, treq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For fiipf lops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
omputed using the above |
-
QUALITY SEMICONDUCTOR INC.
=====
4-145
QS377T, 2377T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500O unless otherwise noted
Symbol
Description
Notes
(1)
377
2377
377A
2377A
377C
2377C
Unit
Min
Max
Min
Max
Min
Max
tPHL
Propagation Delay
CP to Oi, 377
COM
2
13
2
7.2
2
5.2
ns
t PLH
MIL
2
15
2
8.3
Propagation Delay
Or to Ul, 23/7
COM
2
13
2
7.2
2
5.2
MIL
2
15
2
8.3
ts
Data Setup Times
DitoCP
COM
2.5
2
1.5
i 'V-
MIL
3
2
tH
Data Hold Time
DitoCP
COM
2
1.5
1
MIL
2.5
1.5
tsc
Clock Enable Setup
Time, CE to CP
COM
3
2
1.5
MIL
3
2
tHC
Clock Enable Hold Time
CEtoCP
COM
1.5
1.5
1
MIL
1.5
1.5
tWCP
Clock Pulse Width
HIGH or LOW
COM
2
7
6
4
MIL
7
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-146
QUALITY SEMICONDUCTOR INC.
QS521T
Q
High Speed CMOS
8-bit
Comparator
FEATURES/BENEFITS
• QSFCT521B faster than 74F
• lol=48 mA COM, 32 mA MIL
• TTL-compatible input and output levels
• Mil product compliant with MIL-STD 883, Class B
DESCRIPTION
=
QS54/74FCT521T
4.1 ns delay A or B to 01=5" for QSFCT521 D
CMOS power levels < 7.5 mW static
Available in PDIP, ZIP, SOIC, CERDIP, LCC
JEDEC standard pinouts
The QSFCT521AT/BT is a high speed CMOS TTL-compatible 8-bit identity comparator. Two words of
up to eight bits are compared and a low output is provided when the words match. An expansion input
allows the comparason to be extended over multiple words. All inputs have clamp diodes for
undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application
Note AN-001).
FUNCTIONAL BLOCK DIAGRAM
AO
BO
A1 -
B1
A2
B2
A3
as — -j\yv,
B5 —US-'
A6 — ^y>-
B6
A7
11=5
B7
01=5
FCT2xxx only
QUALITY SEMICONDUCTOR INC.
4-147
QS521T
PIN CONFIGURATIONS
PDIP, SOIC, QSOP
ZIP
Ti=5C
AO C
• • •
2
^ 20
19
□ VCC Ta=B (
□ Da=B BO (
BO C
3
18
□ B7
BK
ai r
4
17
□ A7
B2 (
B1C
5
16
□ B6
B3 (
A2C
6
.a
15
□ A6
A4 (
B2 C
7
14
□ B5
A5(
A3 C
8
13
□ A5
A6(
B3 C
9
12
□ B4
A7<
GNDC
10
11
I] A4
ALL PINS TOP VIEW
2 ) AO
4 ) A1
6 ) A2
20 )
INDEX
8
) A3
A1 T
□ 4
10
) GND
B1 I
□ 5
12
) B4
A2J
3 6
14
) B5
B2T
] 7
16
) B6
A3 I
L
18
) B7
LCC
J4[
m
PIN DESCRIPTION
FUNCTION TABLE
Pin Name
I/O
Description
A0-A7
1
Word A
B0-B7
1
WordB
1^=5
1
Expansion Input
Ui=B
o
Compare Output
Inputs
Output
Function
A0-A7, B0-B7
11=5
AO-7 = BO-7
L
L
Compare
Eoual
AO-7 * BO-7
L
H
Compare
Not Equal
X
H
H
Expand Input
Not Valid
4-148 QUALITY SEMICONDUCTOR INC.
QS521T
=
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Numberof Outputs, M=Numberof inputs
CAPACITANCE
< i
.0.5 watts
65°C
TA=25°C, f = 1 MHz,Vin = 0V, Vout = 0V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1-9,11-18
4
4
5
7
PF
19
6
6
7
9
PF
8
8
9
10
PF
Note:
but not tested
i
QUALITY SEMICONDUCTOR INC.
4-149
QS521T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(D
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All inputs
•
0.2
**
I ih|
|H|
Input Current
Input HIGH or LOW
Vcc= MAX
0 < Vin < Vcc
m i i
~,ir -. '
5
uA
|taz|
Off State Output
Current (Hi-Z)
Vcc = MAX, 0 < Vin < Vcc
_
■ ""' *
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
_
mA
Vic
Input Clamp Voltage
Vcc =MIN,lin = 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
Ion = 12 mA (MIL)
2.4
-
-
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-150
QUALITY SEMICONDUCTOR INC.
QS521T
=
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min
Max
Unit
WUlCoL-CllL rUnCt
Supply Current
sjrr - may frpn - 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 c
mA
AlCC
Supply Current per
Input @TT1_ HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vex; = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive toad capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
— — — — — — — — — ■
CTOR INC. 4-151
QS521T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V+1 0%
Cload = 50 pF, Rload - 500O unless otherwise noted. Units are nanoseconds unless otherwise noted.
Symbol
Description
521
521A
521 B
521C
521D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai =Bi to Oa=b
Com
1.5
11
1.5
7.2
1.5
5.5
1.5
4.5
1.5
4.1
ns
Mil
1.5
15
1.5
9.5
1.5
7.3
1.5
5.1
tPHLX
tPLHX
Propagation Delay
la-b to Oa-b
Com
1.5
10
1.5
6
1.5
4.6
1.5
4.1
1.5
3.9
Mil
1.5
9
1.5
7.8
1.5
6.0
1.5
4.5
Notes:
1 . See test circuits and wave forms.
4-152
QSFCT540T, 541 T, 2540T, 2541 T
Q
High Speed CMOS
8-Bit
Buffers/Line Drivers
QS54/74FCT540T
QS54/74FCT541T
QS54/74FCT2540T
QS54/74FCT2541T
FEATURES/BENEFITS
Pin and function compatible to the 74F540/1
74FCT540/1 and 74FCT540T/1T
CMOS power levels: <7.5 mW static
Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T540T/1T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Standard and A speed grades with 5.1 ns tPD for
• lol = 64 mA Com., 48mA Mil.
■
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FC
CT-T 2540T/1T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
A • Std and A speed grades with 5.1 ns tPD for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT540T and QSFCT541T are 8-bit buffers/line drivers with three-state outputs that are ideal
for driving high-capacitance loads as in memory address and data buses. The FCT2540 and FCT2541
are 25ft resistor output versions useful for driving transmission lines and reducing system noise. The
2540 series parts can replace the 540 series to reduce noise in an existing design. All inputs have
clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression (see
QSI Application Note AN-001), and outputs will not load an active bus when Vcc is removed from the
device.
FUNCTIO
FCTS40, 2540
CJFT
CE2
A0(2)
K Y0(18) A4(6)
^>o Y1(17) A5(7) ^ Y5(13)
A2(4)
A3(5)
6) A6(8)
Y3(15) A7(9)
Ko^6L12)
|^7L11)
FCT541/2541
AQi2i_
AU31
Y0(18) A4(6)
Y1(17) A5(7)
A3(5) |l Y3(15)
A6(8)
Y4(14)
Y5(13)
ft) Yfi(1?)
AZ121 ^ Y7(11)
-
QUALITY SEMICONDUCTOR INC.
4-153
QSFCT540T, 541 T, 2540T, 2541 T
=======
PINOUTS
FCT540/541
FCT2540/2541
PDIP, SOIC, QSOP
-
ZIP
AOC 2
A1 C 3
A2 C 4
A3 C 5
A4 C 6
A5 C 7
A6 C 8
A7 C 9
GNDC 10
□ DE2
□ YO
□ Y1
19
18
17
16h Y2
15
14
13
12
11
A1 C
A3 (
A5 C
A7 (
Y7 (
Y5 ( 13
Y3 ( 15
Y1 ( 17
UE2 ( 19
□ Y3
□ Y4
□ Y5
□ Y6
Y7
•■ ■
ALL PINS TOP VIEW
2
5
2 ) AO
4 ) A2
INDEX
6
> A4
r I
8
) A6
A2
□ 4
10
) GND
A3
□ 5
12
) Y6
A4
□ 6
14
) Y4
A5
□ 7
16
) Y2
A6
□ 8
18
) YO
s
m co t-
J4
0> t- -r- y-
FCT540/2540, FCT541/2541
SET
QE2
Input A
540
541
Function
Output Y
Output Y
H
X
X
Hi-Z
Hi-Z
Disable Outputs
X
H
X
Hi-Z
Hi-Z
L
L
L
H
L
Enable Outputs
L
L
H
L
H
H=High, L=Low, Z=High Impedance
asss
4-154
QUALITY SEMICONDUCTOR INC.
QSFCT540T, 541 T, 2540T, 2541 T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to Vrx + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Input Diode Current with V | >VCC 20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Diode Current with Vq >V cc 50 mA
DC Output Current Max. sink current/pin 70 mA
DC Output Current Max. source current/pin 30 mA
Total DC Ground Current (NxlOL +MxAI CC) mA
Total DC VCC Power Supply Current (NxlOH + MxAl CC) mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25°C, f = 1 MHz,Vin = 0V,Vout = 0V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1.19
4
4
5
7
PF
6
6
7
9
pF
2-9,11-18
8
8
9
10
I I
PF
Note: Capacitance is characterized but not tested
■
-
QUALITY SEMICONDUCTOR INC.
4-155
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cum K n 1
o y 1 1 1 uu i
Pa ram At or
rdi aiiiciyi
Tact r^nnHitinnc
1 col V#UIIUIIIUII9
Mln
m i ii
T vn
(D
Max
Unit
Willi
Vih
viri
input niyii voiidyy
Logic HIGH for All Inputs
9 n
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVtt
t\ VI
input riysiensis
Vtlh-Vthl for All Inputs
1*1
|||
Input Current
Input HIGH or LOW
Vcc=MAX
0 < Vin < Vcc
-
5
uA
|bz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX,Vo = GND(2,3)
-60
-
_
mA
lor
Current Drive
FCT2XXX (25Q)
Vcc=Min,Vo=2.0V
50
■ "
mA
Vic
input isidiup vuiidyy
Vcc = MIN, lin = 18 mA (3)
.n 7
-1 0
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
O A
Volts
loh = 15 mA (COM)
O A
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
U.DO
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25fl)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-156
QUALITY SEMICONDUCTOR INC.
QSFCT540T, 541 T, 2540T, 2541 T
=
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
If AAA \ f £ A
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 .5
mA
AlCC
Supply Current per
Input @ TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. Forflipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
-
4-157
QSFCT540T, 541 T, 2540T, 2541 T
==^====5===S========^^^^^
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
FCT540/A, FCT2540/A
Symbol
Description
Notes
540,
2540
540A,
2540A
Unit
Ml
Cc
m
M
II
Cc
m
M
II
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to Yi, 540
1.5
8.5
1.5
9.5
1.5
4.8
1.5
5.1
ns
Propagation Delay
1.5
8
1.5
9
1.5
4.8
1.5
5.1
Ai to Yi, 2540
tPZH
tPZL
Output Enable Time
OE to Yi, 540
1.5
10
1.5
10.5
1.5
6.2
1.5
6.5
Output Enable Time
CE to Yi, 2540
1.5
10
1.5
10.5
1.5
6.2
1.5
6.5
tPHZ
tPLZ
Output Disable Time
OE to Yi
2
1.5
9.5
1.5
12.5
1.5
5.6
1.5
5.9
Notes: 1. Minimum propagation delay values are guaranteed but not tested.
2. This parameter is guaranteed but not tested.
FCT541/A, FCT2541/A
Symbol
Description
Notes
(1)
541, 2541
541 A, 2541 A
Unit
Com
Mil
Com
Mil
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to Yi, FCT541
1.5
8
1.5
9
1.5
4.8
1.5
5.1
ns
Propagation Delay
Ai to Yi, FCT2541
1.5
8
1.5
9
1.5
4.8
1.5
5.1
tPZH
tPZL
Output Enable Time
OE to Yi, FCT541
1.5
10
1.5
10.5
1.5
6.2
1.5
6.5
Output Enable Time
'DE'toYi, FCT2541
1.5
10
1.5
10.5
1.5
6.2
1.5
6.5
tPHZ
tPLZ
Output Disable Time
OE to Yi
2
1.5
9.5
1.5
12.5
1.5
5.6
1.5
5.9
Notes:
1 . Minimum propagation delay values are guaranteed but not tested.
2. This parameter is guaranteed but not tested.
4-158
QUALITY SEMICONDUCTOR INC.
=
QSFCT543T, 544T, 2543T, 2544T
Q
High Speed CMOS
8-bit Bus Interface
LatchTransceivers
QS54/74FCT543T
QS54/74FCT544T
QS54/74FCT2543T
QS54/74FCT2544T
FEATURES/BENEFITS
• Pin and function compatible to the 74F543/4
74FCT543/4 and 74FCT543T/4T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 543T/4T
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3. 5 V
Military product compliant to MIL-STD-883
JEDEC-FCT spec compatible
Fastest CMOS logic family available
Std, A and C speed grades with 5.5ns tPD fi
lol = 64 mA Com., 48mA Mil.
orC
FCT-T
2543T. . .
Built-in 25Q series resistor outputs reduce
reflection and other system noise
Std and A speed grades with 6.5ns tPD for A
lol = 12mA Com.
DESCRIPTION
The QSFCT543T/4T and QSFCT543T/4T are 8-bit high-speed CMOS TTL-compatible latched bus
transceivers with three-state outputs that are ideal for driving high capacitance loads such as memory
and address buses. The 2543/4 devices are 25£2 resistor output versions useful for driving transmission
lines and reducing system noise. The 2543 series parts can replace the 543 series to reduce noise in an
existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs have
ground bounce suppression (see QSI Application Note AN-001), and outputs will not load an active bus
when Vcc is removed from the device.
■
FUNCTIONAL BLOCK DIAGRAM
QSFCT543T, 544T, 2543T, 2544T
PINOUTS
PDIP, SOIC, QSOP
inde:
L~EBA
UEBA
AO
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
c
1
24
vcc
□ CEBA
c
2
23
□ BO
c
3
22
□B1
c
4
21
^ B2
c
5
20
^ B3
c
6
19
□ B4
c
18
^ B5
c
8
17
3 B6
c
9
16
□B7
c
10
15
□ CEAB
c
11
14
^OEAB
12
11
! ^ ? K ffl Tf N O 8
i_i cq co m cq >
< < < < o
j s s s si a
ZIP
«- co in
CD
<r<<<K«tticocD (jj
UJ
ALL PINS TOP VIEW
PIN DESCRIPTIONS
Name
I/O
Description
A1-A8
I/O
A Bus
B1-B8
I/O
B Bus
CEAB
Chip Select, A to B
CEBA
Chip Select, B to A
CEAB
Latch Enable, A to B
CEBA
Latch Enable, B to A
OEAB
Output Enable, A to B
UEBA
Output Enable, B to A
4-160
QUALITY SEMICONDUCTOR
QSFCT543T, 544T, 2543T, 2544T
FUNCTION TABLES - QSFCT543/4, 2543/4
Inputs
Outputs
Function
CESB
CEBS
CESB
LEEK
A1-8
B1-8
543/2543
544/2544
H
H
Z
Z
Disabled, Hold
Disabled, Hold
H
H
z
z
Disabled
Disabled
"
H
H
NC
NC
Hold
Hold
:
L
H
A->B Latch Open
A->B Latch Open
H
L
B->A Latch Open
B->A Latch Open
L
H
A Latch -> B Bus
A Latch->"B"Bus
H
L
B Latch -> A Bus
B Latch ->"^ Bus
H
= HIHH
-
L
NC =
= LOW
= No Change
= High Impedar
QUALITY SEMICONDUCTOR INC.
4-161
QSFCT543T, 544T, 2543T, 2544T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with V0 <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
■ajs B"<-r,;;;eJ A ! «u8 8 < riois J A i - "I I u "j ,
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
4
4
5
7
PF
6
6
7
9
PF
1-11,13-23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
■
4-162
QUALITY SEMICONDUCTOR INC.
QSFCT543T, 544T, 2543T, 2544T
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C. Vcc=5.0V+5% Military TA=-55°C to 125°C, VCC=5.0V±10%
Symbol
Parameter
Min
Typ
(D
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
input lvjvv voiiayc
Logic LOW for All Inputs
0.8
AVt
Inmit I— 1\ jet a r\ c \e
inpui rtysiciisis
Vtlh - Vthl for All Inputs
-
0.2
I lih I
|HJ
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
UA
|loz|
Off State Output
Current (Hi-Z)
Vcc = M
AX,0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX (25£i)
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lot = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25£1)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
1 . Typical values indicate V^S.OV and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-163
QSFCT543T, 544T, 2543T, 2544T
■
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-164
QUALITY SEMICONDUCTOR INC.
QSFCT543T, 544T, 2543T, 2544T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Cload = 50 pF, Rload = 500£i unless otherwise noted
Symbol
Description
543/4,
2543/4
543/4A,
2543/4A
543C
•
o
Com
MM
Com
MM
Com
MM
z
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tPHLB
tPLHB
Bus to Bus
Delay
I atrho<;
L a t U 1 IWa
543
2.5
8.5
2.5
10
2.5
6.5
2.5
7.5
2.5
5.5
ns
544
2.5
8.5
2.5
10
2.5
6.5
2.5
7.5
Open
(Transparent)
2543
2.5
8.5
2.5
10
2544
2.5
8.5
2.5
10
tPHLL
tPLHL
Latch Enable
to Data Delay
LEAB, LEBA
543
2.5
12.5
2.5
14
2.5
8
2.5
9
2.5
7.0
544
2.5
12.5
2.5
14
2.5
8
2.5
9
to
A, B Bus
2543
2.5
12.5
2.5
14
2544
2.5
12.5
2.5
14
tPZH
tPZL
Output
Enable Time
cjeatt, otba
543
2
12
2
14
2
9
2
10
2.0
8.0
544
2
12
2
14
2
9
2
10
CEAB,"CET3A
to A, B Bus
2543
2
12
2
14
2544
2
12
2
14
tPHZ
tPLZ
Output Disable Time
2
2
9
2
13
2
7.5
2
8.5
2
6.5
ts
Setup Time
An to LEAB,
Bn to LEBA
3
3
2
2
2
tH
Hold Time
An to LEAB,
Bn to LEBA
2
2
2
2
2
tw
Pulse Width Low
LEAB or LEBA
5.0
5.0
5.0
5.0
5.0
Notes:
1 ) See Test Circuit and Waveforms. Minimums Guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-165
QSFCT543T, 544T, 2543T, 2544T
4-166
QUALITY SEMICONDUCTOR INC.
QSFCT573T, 2573T
Q
High Speed CMOS
Bus Interface
8-bit Latches
QS54/74FCT573T
QS54/74FCT2573T
FEATURES/BENEFITS
• Pin and function compatible to the 74F573
74FCT573 and 74FCT573T
• CMOS power levels: <7.5 mW static
■ Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T573T
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Military product compliant to MIL-STD-883
■
JEDEC-FCT spec compatible
Fastest CMOS logic family available
Std, A, and C speed grades with 4.7 ns tPD for C
lol = 48 mA Com., 32 mA Mil.
FCT-T 2573T
Built-in 25a series resistor outputs reduce
reflection and other system noise
Std and A speed grades with 5.2 ns tPD for A
lol = 12mA Com.
DESCRIPTION
The QSFCT573T and QSFCT2573T are 8-bit high-speed CMOS TTL-compatible buffered latches with
three-state outputs that are ideal for driving high capacitance loads such as memory and address buses.
The 2573 devices are 25Q resistor output versions useful for driving transmission lines and reducing
system noise. The 2573 series parts can replace the 573 series to reduce noise in an existing design.
All inputs have clamp diodes for undershoot noise suppression. All outputs have ground bounce
:ation Note AN-001), and outputs will not load an active bus when Va
removed from the device.
FUNCTIONAL BLOCK DIAGRAM
FCT573
DATA Di —
LATCH ENABLE LE
OUTPUT ENABLE 5E
>
25Q.
Oi
FCT2xxx only
QUALITY SEMICONDUCTOR INC.
4-167
QSFCT573T, 2573T
PINOUTS
PDIP, SOIC, QSOP
ALL PINS TOP VIEW
PIN DESCRIPTIONS
FUNCTION TABLE
Name
I/O
Description
Di
1
Data Inputs
Oi
0
Data Outputs
LE
1
Latch Enable
1
Output Enable
Inputs
Internal
Q
Value
Outputs
Function
OE
LE
Di
Oi
H
X
X
X
z
Disable Outputs
L
X
X
L
L
Enable Outputs
L
X
X
H
H
X
H
L
L
X
Pass Input Data
X
H
H
H
X
L
L
X
Q
X
Hold Prior Data
4-168
QUALITY SEMICONDUCTOR INC.
QSFCT573T, 2573T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground
.. -0.5Vto+7.0V
)C Output Voltage VQ -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V(<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature -65° to +165°C
CAPACITANCE
TA=25°C, f=1 MHz.Vin*
0V, Vout = 0 V
I 7T,
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
7
PF
1-9, 11
4
4
5
■
12-19
6
6
7
9
PF
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY
=
QSFCT573T, 2573T
^ — — — — — — — -
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, Vcc=50V+1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
' -
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
-
-
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
0.2
|lih|
|lil|
Input Current
Input HIGH or LOW
Vcc = MAX
0<:Vin<Vcc
-
5
uA
|toz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-DU
mA
lor
mA
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
DU
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
_
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (250)
Vcc = MIN
lol= 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq-S.OV and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-170
QUALITY SEMICONDUCTOR INC.
QSFCT573T, 2573T
POWER SUPPLY CH
i
Symbol
1 1
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
innlv irront
oupfjiy \_/uutJiu
Vcc=MAX, freq = 0
nV<Vin<n ?V est Vrr-0 ?V<Vin<\/fv
1.5
mA
AlCC
Supply Current per
Input @ TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
i values specified under DC specifications.
1 . For conditions shown as MIN or I
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
!
i
QUALITY
INC.
4-171
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Description
Notes
hi
V 1 1
573
2573
573A
2573A
573C
Unit
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Data to Oi, 573
COM
1.5
8
1.5
5.2
1.5
4.7
ns
MIL
2
8.5
1.5
5.6
Propagation Delay
Data to Oi, 2573
COM
1.5
8
1.5
5.2
1.5
4.7
MIL
2
8.5
1.5
5.6
tPHLE
tPLHE
Propagation Delay
LE high to Oi, 573
COM
2
13
2
8.5
2
6.9
MIL
2
14
2
9.8
Propagation Delay
LE high to Oi, 2573
COM
2
13
2
8.5
2
6.9
MIL
2
14
2
9.8
tPZH
tPZL
Output Enable Time
OT to Yi, 573
COM
1.5
11
1.5
6.5
1.5
5.5
MIL
1.5
12.5
1.5
7.5
Output Enable Time
OE to Yi, 2573
COM
1.5
11
1.5
6.5
1.5
6.5
MIL
1.5
12.5
1.5
7.5
tPHZ
tPLZ
Output Disable Time
75E"toYi
COM
2
1.5
7
1.5
5.5
1.5
5.0
MIL
2
1.5
8.5
1.5
6.5
ts
Data Setup Time
Di to LE hi to low
COM
2
2
2
MIL
2
2
tH
Data Hold Time
Di to LE hi to low
COM
1.5
1.5
1.5
MIL
1.5
1.5
tw
LE Pulse Width
HIGH or LOW
COM
2
6
5
4
MIL
2
6
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not
2) This parameter is guaranteed by design but not tested.
4-172 QUALITY SEMICONDUCTOR INC.
QSFCT574T, 2574T
Q
FEATURES/BENEFITS
High Speed CMOS
Bus Interface
rs
iste.
QS54/74FCT574
QS54/74FCT2574
=
=
• Pin and function compatible to the 74FCT574
and 74FCT574T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 574
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std., A, and C speed grades with 5.2ns tPD for C
• lol = 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3. 5 V
Military product compliant to MIL-STD-883
FCT-T 2574
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
■ Std., A, & C speed grades with 6.5ns tPD for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT574/A and QSFCT2574/A are 8-bit high-speed CMOS TTL-compatible buffered registers
with three-state outputs that are ideal for driving high capacitance loads such as memory and address
buses. The 2574 devices are 25ft resistor output versions useful for driving transmission lines and
reducing system noise. The 2574 series parts can replace the 574 series to reduce noise in an existing
design. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground
bounce suppression (see QSI Application Note AN-001), and outputs will not load an active bus when
Vcc is removed from the device.
I !
—
=
FUNCTIONAL BLOCK DIAGRAM
DATA Di
CLOCK CP
FCT574
OUTPUT ENABLE 0"E"
>
25£2
Oi
FCT2xxx only
QUALITY SEMICONDUCTOR INC. 4-173
QSFCT574T, 2574T
PINOUTS
PDIP, SOIC, QSOP
ALL PINS TOP VIEW
■ r cOMo but
PIN DESCRIPTIONS
Name
I/O
Description
Di
1
Data Inputs
Oi
0
Data Outputs
CP
1
Clock Input
OE
1
Output Enable
FUNCTION TABLE
Inputs
0~E
CP
DI
Internal
Q
Value
Outputs
Oi
Function
Disable Outputs
Enable Outputs
Load Input Data
;
4-174
QUALITY SEMICONDUCTOR INC.
QSFCT574T, 2574T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7j
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with V0 <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
TSTGStorage Tempelat^
CAPACITANCE
TA = 25°C, f = 1 MHz, Vin = 0V, Vout = 0 V
QUALITY SEMICONDUCTOR INC.
4-175
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCc=50V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
P )
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
I Oil
I HI
Input Current
Input HIGH or LOW
Vcc=MAX
0 < Vin < Vcc
5
uA
|bz|
Off State Output
Current (Hi-Z)
Vcc = MAX, 0 5Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
-
-
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
-
-
Volts
loh = 15 mA (COM)
2.4
-
-
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
-
-
0.50
lol = 48 mA (COM)
-
-
0.50
Output LOW Voltage
FCT2XXX (25£2)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25£2)
VCC = MIN
k>l = 12 mA (MIL)
21
28
38
lol= 12 mA (COM)
24
28
35
Notes: 1. Typical values indicate VcC=5.0V and Ta=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-176
QUALITY SEMICONDUCTOR INC.
QSFCT574T, 2574T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
ICC
Quiescent Power
Supply Current
\/rv* MAY fron A
vec = max, treq = o
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 e;
1 -O
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified i
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
■
QSFCT574T, 2574T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(1 )
574
2574
574A
2574A
574C
Unit
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
CP to Oi, 574
COM
2
10
2
6.5
2
5.2
ns
MIL
2
11
2
7.2
2
6.2
Propagation Delay
CP to Oi, 2574
COM
2
10
2
6.5
MIL
2
11
2
7.2
tPZH
tPZL
Output Enable Time
OE to Yi, 574
COM
1.5
12.5
1.5
6.5
1.5
5.5
MIL
1.5
14
1.5
7.5
1.5
6.2
Output Enable Time
OE to Yi, 2574
COM
1.5
12.5
1.5
6.5
MIL
1.5
14
1.5
7.5
tPHZ
tPLZ
Output Disable Time
OEtoYi
COM
2
1.5
8
1.5
5.5
1.5
5
MIL
2
1.5
8
1.5
6.5
1.5
5.7
ts
Data Setup Time
DitoCP
COM
2
2
2
MIL
2
2
2
tH
Data Hold Time
DitoCP
COM
2
1.5
1.5
MIL
2
1.5
1.5
tw
Clock Pulse Width
HIGH or LOW
COM
2
7
5
5
MIL
2
7
6
6
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
4-178
QUALITY SEMICONDUCTOR INC.
QSFCT646T, 648T, 2646T, 2648T
High Speed CMOS
8-bit Bus Interface
Register Transceivers
FEATURES/BENEFITS
• Pin and function compatible to the 74F646/8
74FCT646/8 and 74FCT646T/8T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T 646T/8T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• A, C and D speed grades with 4.8ns tPD for D
• lol = 64 mA Com., 48 mA Mil.
QS54/74FCT646T
QS54/74FCT648T
QS54/74FCT2646T
QS54/74FCT2648T
=====
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Military product compliant to MIL-STD-883
FCT-T 2646T/8T
• Built-in 25£2 series resistor outputs reduce
reflection and other system noise
• Std, A, & C speed grades with 5.4ns tPD for C
• lol = 12mA Com.
=
=
=
DESCRIPTION
The QSFCT646T/8T and QSFCT646T/8T are 8-bit high-speed CMOS TTL-compatible registered bus
transceivers with three-state outputs that are ideal for driving high capacitance loads such as memory
and address buses. The 2646/8 devices are 250 resistor output versions useful for driving transmission
lines and reducing system noise. The 2646 series parts can replace the 646 series to reduce noise in an
existing design. All inputs have clamp diodes for undershoot noise suppression. All outputs have
ground bounce suppression (see QSI Application Note AN-001), and outputs will not load an active bus
when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
w
m
648 only.
646 outputs
are noninverting
CBA
BBUS
4-179
PDIP, SOIC, QSOP
CAB
p
1
1
W 24
VCC
SAB
p
CO
1/tsA
DIR
p
F
3
SBA
A1
4
CI
G
A2
i_
5
20
—
B1
A3
p
o
1Q
i y
no
A4
p
7
18
B3
A5
c
8
17
B4
A6
E
9
16
B5
A7
c
10
15
B6
A8
c
11
14
B7
GND
c
12
13
B8
co co o < <
EC < < O O CO CO
S w O Z > O CO
CD
r-~ oo
< <
<i-comi-.Z.i*-tf>coi-caa
w<<<<OcocnmcQW>
r 1 ao r- co
z co m m
t- co m
u u u u u u
o CM i
ZIP '
„ m in
O) 1— T— V—
^1 KJ
CM <5
CM
ALL PINS TOP VIEW
m (J CM ^ CO 00 ©
<S<<<<mmiricQ g
PIN DESCRIPTIONS
Name
I/O
Description
A1-A8
I/O
A Bus
B1-B8
I/O
B Bus
CAB
Clock A to Register
CBA
Clock B to Register
SAB
A Bus or Reg to B
SBA
B Bus or Reg to A
DIR
Direction, A->B or B->A
G
Output Enable
4-180
QUALITY SEMICONDUCTOR INC.
QSFCT646T, 648T, 2646T, 2648T
FUNCTION TABLES - QSFCT646/8, 2646/8
Inputs
Outputs
Function
DIR
CAB
CBA
SAB
SBA
A1-8
B1-8
646/2646
648/2648
H
Z
Z
Disabled
Disabled
L
L
— - —
— - —
A
Z
UUtpUt A
UUtpUt A
L
H
Z
B
Output B
Output B
T
Load A Reg
Load A Reg
T
Load B Reg
L
A Bus -> B Bus
"A Bus -> B Bus
H
A Reg -> B Bus
"A" Reg -> B Bus
L
B Bus -> A Bus
"B Bus -> A Bus
H
— "- —
B Reg -> A Bus
U Reg -> A Bus
H =HIGH
L = LOW,
Z = High Impedance
s
QUALITY SEMICONDUCTOR INC.
4-181
QSFCT646T, 648T, 2646T, 2648T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage VQ -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstoraSe Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
4
4
5
7
pF
6
6
7
9
PF
1-11,13-23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
4-182
=
QUALITY SEMICONDUCTOR INC.
QSFCT646T, 648T, 2646T, 2648T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(D
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
I lih I
| llll |
llill
Input Current
Input HIGH or LOW
Vcc= MAX
0<SVin< Vcc
5
uA
llozl
Vcc = MAX,0,Vin,Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX (250)
VCC = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc =MIN,lin= 18 mA (3)
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25£2)
VCC = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
Q
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq^.OV and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-183
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V£Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
-
2.0
Qccd
Supply Current per
input per mHz
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
-
4-184
QUALITY SEMICONDUCTOR INC.
QSFCT646T, 648T, 2646T, 2648T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 125°C, VCC=5.0V±10%
Cload = 50 pF, Rload = 500fl unless otherwise noted
FCT646, FCT2646
Symbol
I 1
Description
Notes
d)
646,
2646
646A,
2646A
646C,
2646C
646 D,
2646D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPHLB
t PI HR
I ri_nD
Bus to Bus
Delay 646
Com
2
9
2
6.3
1.5
5.4
1.5
4.8
ns
Mil
2
11
2
7.7
1.5
6.0
Bus to Bus
Delay 2646
Com
2
9
2
6.3
1.5
5.4
Mil
2
11
2
7.7
1.5
6.0
tPZH
tP7l
Output Enable
Time 646
Com
2
14
2
9.8
1.5
7.8
1.5
7.3
Mil
2
15
2
10.5
1.5
8.9
Output Enable
Time 2646
Com
2
14
2
9.8
1.5
7.8
Mil
2
15
2
10.5
1.5
8.9
tPHZ
tPLZ
Output Disable
Time
Com
2
2
9
2
6.3
1.5
6.3
1.5
6.3
Mil
2
2
11
2
7.7
1.5
7.7
tPHLC
t pi Hn
Clock to Bus
Delay 646
Com
2
9
D.O
1.5
5.7
1.5
5.2
Mil
2
10
2
7
1.5
6.3
Com
2
9
2
6.3
1.5
5.7
Mil
2
10
2
7
1.5
6.3
tPHLS
t PI H"?
SBA/SAB to Bus
Delay 646
Com
- •
2
11
2
7.7
1.5
6.2
1.5
5.8
Mil
2
12
2
8.4
1.5
7.0
SBA/SAB to Bus
Delay 2646
Com
2
11
2
7.7
1.5
6.2
Mil
2
12
2
8.4
1.5
7.0
ts
Data Setup Time
Com
4
2
2
2
L_
Mil
4.5
2
2
tH
Data HoldTir
ne
Com
2
1.5
1.5
1.5
Mil
2
1.5
1.5
tPWH
tPWL
Clock Pulse Width
High or Low
Com
2
6
5
5
5
Mil
2
6
5
5
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
' SEMICONDUCTOR INC. 4-185
QSFCT646T, 648T, 2646T, 2648T
FCT648, FCT2648
Symbol
Description
Notes
(1)
648,
2648
648A,
2648A
648C,
2648C
Min
mill
Mav
mew
Min
May
Max
Min
May
tPHLB
tPLHB
Bus to Bus
Delay 648
Com
o
£
O
O
o
£
ft A
O.D
1 ft
i .0
ft A
Mil
Mil
o
m
Q
£
0 .O
1 ft
ft n
D.U
Com
Q
O
ft ft
1 ft
Bus to Bus
Delay 2648
o
c
O
£.
ft A
Ml 1
Ml 1
o
Q
o
e
D.O
1 ft
ft n
D.U
tPZH
tPZL
Output Enable
Time 648
Com
o
e
ID
O
e
1 ft
7 a
/ .0
Mil
Mil
£.
1 o
o
E
1 O ft
1 £.D
1 ft
P Q
o.y
Output Enable
Time 2 648
Com
2
15
2
10.5
1 .5
7.8
Mil
Mil
2
18
2
12.6
1.5
8.9
tPHZ
tPLZ
Output Disable
Time
Com
2
o
e
y
2
6.3
1 .0
ft Q
D.O
mii
Mil
2
o
c
o
S
7 7
1 ft
7 7
tPHLC
tPLHC
Clock to Bus
Delay 648
tom
o
c.
Q
o
B
1 ft
1 .0
ft 7
Mil
MII
c.
1U
o
£.
/
1 c
D.O
Clock to Bus
Delay 2648
Com
2
9
6.3
1 .5
5./
Mil
Mil
2
10
2
7
1 .5
6.3
tPHLS
t PLUS
CD A fC A D ♦« Duo
odA/oAd to bUS
Delay 648
Com
p
ft 0
Mil
2
12
2
8.4
1.5
7.0
SBA/SAB to Bus
Delay 2648
Com
2
11
2
7.7
1.5
6.2
Mil
2
12
2
8.4
1.5
7.0
ts
Data Setup Time
Com
4
2
2
Mil
4.5
2
2
tH
Data Hold Time
Com
2
1.5
1.5
MII
2
1.5
1.5
tPWH
tPWL
Clock Pulse Width
High or Low
Com
2
6
5
5
Mil
2
6
5
5
Unit
Notes:
1 ) See Test Circuit and Waveforms.
2) This parameter is guaranteed by
Minimums guaranteed
design but not tested.
but not tested.
4-186
QUALITY SEMICONDUCTOR INC.
QSFCT651T, 652T, 2651 T, 2652T
High Speed CMOS
8-bit Bus Interface
er Transceivers
SBC
QS54/74FCT651T
QS54/74FCT652T
QS54/74FCT2651T
QS54/74FCT2652T
FEATURES/BENEFITS
• Pin and function compatible to the 74F651/2
74FCT651/2 and 74FCT651T/2T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T651T/2T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std., A and C speed grades with 5.4 ns tPD for C
• lol = 64 mA Com., 48 mA Mil.
TTL -compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-f
FCT-T 2651 T/2T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 6.3 ns tPD for A
• lol = 12mA Com.
DESCRIPTION
1 he QSFCT651T/2T and QSFCT651T/2T are 8-bit high-speed CMOS TTL-compatible registered bus
transceivers with three-state outputs that are ideal for driving high capacitance loads such as memory
and address buses. The 2651/2 devices are 25fl resistor output versions useful for driving
transmission lines and reducing system noise. The 2651 series parts can replace the 651 series to
reduce noise in an existing design. All inputs have clamp diodes for undershoot noise suppression. All
outputs have ground bounce suppression (see QSI Application Note AN-001), and outputs will not load
an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
A BUS
GAB
SBA
CBA »{> REGISTER
BBUS ^ f-
651 only.
652 outputs
are noninvertins
QUALITY SEMICONDUCTOR INC.
4-187
PDIP, SOIC, QSOP
CAB C
SAB C
GAB □
A1 C
A2 C
A3 □
A4 C
A5 C
A6 C
A7 C
A8 C
GND C
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
□ VCC
□ CBA
□ SBA
□ GBS
□ B1
□ B2
□ B3
□ B4
□ B5
□ B6
□ B7
□ B8
m m m u < <
< < < O o cd m
O CO O Z > O CO
TO CM »-
A1 I
3 5
25 L
r GBS
A2 I
3 6
24 C
E B1
A3 I
3 7
23 C
L B2
NC I
1 8
LCC
22 L~
I NC
A4l
3 9
21 L"
L B3
A5I
D10
20 C
Otf
A6l
3 11
19L"
I B5
CM
to in <o oo
m
Q < „
<t-cowi^Zi--incoi-caa
co<<<<Ocammmco>
CM
1— T- T- T- CM
3 O CM
zfp
— T" «
81
t- to 10 r~
5 5
o a
Si 2 3 S
CO CO
m m 1
■
CM
m
2
o
ALL PINS TOP VIEW
PIN DESCRIPTIONS
Name
I/O
Description
A1-A8
I/O
A Bus
B1-B8
I/O
B Bus
CAB
Clock A to Register
CBA
Clock B to Register
SAB
A Bus or Reg to B
SBA
B Bus or Reg to A
GAB
Enable A to B
Enable B to A
4-188
QUALITY SEMICONDUCTOR INC.
QSFCT651T, 652T, 2651 T, 2652T
FUNCTION TABLES - QSFCT651/2, 2651/2
Inputs
Outputs
Function
GAB
GBS
CAB
CBA
SAB
SBA
A1-8
B1-8
651/2651
652/2652
L
H
-
-
-
-
Z
Z
Disabled
Disabled
L
L
-
-
-
-
A
Z
Output A
Output A
H
H
-
-
-
-
Z
B
Output B
Output B
H
L
A
B
Output A & B
Output A & B
t
Load A Reg
Load A Reg
T
Load B Reg
Load B Reg
L
"A" Bus -> BBus
A Bus -> B Bus
H
IT Reg -> B Bus
A Reg -> B Bus
L
TJ Bus -> A Bus
B Bus -> A Bus
—
L_J
H
TTReg -> A Bus
B Reg -> A Bus
t
H
= HIGH
L = LOW,
Z = High Impedance
QUALITY SEMICONDUCTOR INC.
4-189
QSFCT651T, 652T, 2651 T, 2652T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (tor a pulse width <20 ns) -3.0V
DC Input Diode Current with V(<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
4
4
5
7
PF
6
6
7
9
PF
1-11,13-23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
4-190
QUALITY SEMICONDUCTOR INC.
QSFCT651T, 652T, 2651T, 2652T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCc=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
|tfh|
I lii I
I I
Input Current
Inniit HlfiH or I OW
input nnjn ui i—wvv
Vcc = MAX
II 1
0 < Vin < Vcc
-
-
5
uA
|loz|
Off State Output
dirrpnt (Hi-7^
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
VCC = MAX, Vo = GND (2,3)
-60
-
-
mA
lor
Current Drive
FCT2XXX (25fl)
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc=MIN,lin = 18mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 12 mA (MIL)
2.4
Volts
loh = 15 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 48 mA (MIL)
0.55
lol = 64 mA (COM)
0.55
Output LOW Voltage
FCT2XXX (25£2)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
£1
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-191
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
toe
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2VsVin<Vcc
1.5
mA
Aloe
Supply Current per
Input @TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
-
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-192
QUALITY SEMICONDUCTOR INC.
QSFCT651T, 652T, 2651 T, 2652T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(1)
651/2
2651/2
651/2 A,
2651/2 A
651/2 C,
2651/2 C
Unit
Min
Max
Min
Max
Min
Max
tPHLB
t PLHB
Bus to Bus
Com
2
9
2
6.3
1.5
5.4
ns
Delay 651
Mil
2
10
2
6.7
1.5
6.0
Bus to Bus
Com
2
9
2
6.3
Delay 2651
Mil
2
10
2
7.7
tPZH
Output Enable
Com
2
10
2
9.8
1.5
7.8
Time 651
Mil
2
12
2
10.5
1.5
8.9
Output Enable
Com
2
10
2
9.8
Time 2 651
Mil
2
12
2
10.5
tPHZ
tPI 7
Output Disable
Time
Com
2
2
9
2
6.3
1.5
6.3
MM
2
2
12
2
7.7
1.5
7.7
tPHLC
t PLHC
Clock to Bus
Com
2
9
2
6.3
1.5
5.7
Delay 651
Mil
2
10
2
7
1.5
6.3
Clock to Bus
Com
2
9
2
6.3
Delay 2651
Mil
2
11
2
7
tPHLS
SBA/SAB to Bus
Com
2
11
2
7.7
1.5
6.2
tPLHS
Delay 651
Mil
2
12
2
8.4
1.5
7.0
SBA/SAB to Bus
Com
2
11
2
7.7
Delay 2651
Mil
2
12
2
8.4
ts
Data Setup Time
Com
4
2
2
Mil
4.5
2
2
tH
Data Hold Time
Com
2
1.5
1.5
Mil
2
1.5
1.5
tPWH
tPWL
Clock Pulse Width
Com
2
6
5
5
High or Low
Mil
2
6
5
5
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
=
=====
QUALITY SEMICONDUCTOR INC.
QSFCT651T, 652T, 2651 T, 2652T
...
4-194
QSFCT821/3/5T, 2821 /3/5T
=
Q
High Speed CMOS
Bus Interface
8, 9 & 10-bit
Registers
QS54/74FCT821T
QS54/74FCT823T
QS54/74FCT825T
QS54/74FCT2821T
QS54/74FCT2823T
QS54/74FCT2825T
_
=
FEATURES/BENEFITS
• Pin and function compatible to the 74F821/3/5
74FCT821/3/5 and 74FCT821T/3T/5T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
■ Undershoot clamp diodes on all inputs
FCT 821T/3T/5T
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT 2821T/3T/5T
JEDEC-FCT spec compatible
Fastest CMOS logic family available
lol = 48 mA Com., 32 mA Mil.
Built-in 25Q series resistor outputs reduce
reflection and other system noise
lol = 12 mA Com.
=
=
DESCRIPTION
The QSFCT821T/823T/825T and QSFCT821T/823T/825T are 10, 9, and 8-bit high-speed CMOS TTL-
compatible buffered registers with three-state outputs that are ideal for driving high capacitance loads
such as memory and address buses. The 2821/3/5 devices are 25Q resistor output versions useful for
driving transmission lines and reducing system noise. The 2821 series parts can replace the 821 series
to reduce noise in an existing design. All inputs have clamp diodes for undershoot noise suppression.
All outputs have ground bounce suppression (see QSI Application Note AN-001), and outputs will not
load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
CLOCK ENABLE (EN)
DATA IN (Di)
CLEAR (CLR)
CLOCK (CP)
OUTPUT ENABLE OE
FCT2xxx only
DATA OUT (Yi)
PINOUTS
FCT821 PIN CONFIGURATIONS
FCT821 - 10-BIT REGISTER
PDIP, SOIC, QSOP
UE
DO
D1
D2
D3
C 1
C 2
C 3
c
D4 C 6
D5 [ 7
D6 C 8
D7 C 9
c
GND C 12
D8
D9
10
11
INDE
24 □ VCC
23 □ Y0
22 □ Y1
21 IlY2
20 □ Y3
19 □ Y4
18 □ Y5
17 □ Y6
16 □ Y7
15 □ Y8
14 □ Y9
13 P CP
Q O
o w 5 <o co Z o> h id n i- O
QQQQQO>>->->->>
<O»OtMt<£>00OCMTf
i- B ID
WWW
y- m U)
W W W W W W W
o
iii^ninsoiiiotitpi
Kqqqqqo>->->->-
All packages are shown with the Top view
FCT821 LOGIC SYMBOL
D2 I
J 5
D3l
3 6
D4I
3 7
NCI
3 8
D5I
3 9
D6l
□ 10
D7T
3 11
25 L
E Y2
24 C
I Y3
23 C
I Y4
22 C
5 NC
21 C
L Y5
20 C
I Y6
19 C
I Y7
PIN DESCRIPTIONS
FCT821
D
Q
10
CP
CP-
"OE-
iv10
Name
I/O
Function
a
I
Data Inputs
Yi
0
Data Outputs - Three State
CP
I
Clock Pulse
OE
I
Output Enable
4-196
QUALITY SEMICONDUCTOR INC.
QSFCT821/3/5T, 2821/3/5T
FCT823 - 9- BIT REGISTER
PDIP, SOIC, QSOP
INDE
5 § to
-
D2T
■* CO
] 5
CM ^ CO
S3
8
25 C
L Y2
D3I
D4 X
] 6
] 7
24 C
23 C
I Y3
r Y4
NCI
] 8
LCC
22 C
INC
D5I
] 9
21 C
L Y5
D6I
] 10
20 n
I Y6
D7T
] 11
19L"
I Y7
cm m
* in CO
CO
r
O CM CD CO
Q Q Q Q Q
* G | z o E ^
Tt CO 00
t- o m cn
■r- co m
All packages are shown with the Top view
FCT823 LOGIC SYMBOL
PIN DESCRIPTIONS
Name
I/O
Function
Di
1
Data Inputs
Yi
0
Data Outputs - Three State
OE
1
Output Enable
CP
1
Clock Pulse
ER
1
Clock Enable
cm
1
Asynchronous Reset
QUALITY SEMICONDUCTOR INC.
4-197
QSFCT821/3/5T, 2821 /3/5T
FCT825 - 8-BIT REGISTER
PDIP, SOIC, QSOP
DIET C 1
0~E2 C 2
DO C 3
D1 C 4
D2 C 5
D3 C 6
D4 C 7
D5 C 8
D6 C 9
D7 C 10
cm c 11
GND C 12
inde:
24 □ VCC
23 □ SE3
22 □ Y0
21 IlY1
20 □ Y2
19 □ Y3
18 □ Y4
17 □ Y5
16 □ Y6
15 □ Y7
14 □ ER
13 □ CP
KM It- O I"
O UJ UJ <•-> (J Ul _
□ b b ^ > b ?
D1 1
□ 5
D2 J
□ 6
D3 1
□ 7
NCJ
□ 8
D4]
□ 9
D5 J
□ 10
D6 J
□ 11
25 C
r yi
24 C
L Y2
23 C
L Y3
22 £
LNC
21 C
L Y4
20 C
L Y5
19C
?Y6
ICVl Q O
fUrniOSZeiDtfNoO
IOQQQQC0liJ>?>:>>
K->
S & 5 S=
CO GO
ZIP
J » ? 8 SI
uuuuuuuu
P P r m
»j r- >■ > > ixi
*■> b
All packages are shown with the Top View
FCT825 LOGIC SYMBOL
r
-
PIN DESCRIPTIONS
I FCT825
D Q
CP EN CLR
Yi
CP
CLR
OE1
OE2
OE3
Name
I/O
Function
Di
I
Data Inputs
Yi
o
Data Outputs - Three State
UE
I
Output Enable
CP
I
Clock Pulse
ER
I
Clock Enable
CCR
I
Asynchronous Reset
4-198
QUALITY SEMICONDUCTOR INC.
QSFCT821/3/5T, 2821 /3/5T
FUNCTION TABLES - QSFCT821/823/825
Inputs
Int.
O/P
Function
0~E
CCR
EN
Dl
r p
Ql
Yl
H
X
L
L
T
1
L
z
HighZ
H
X
L
H
i
H
z
H
L
X
X
X
L
z
Clear
L
L
X
X
X
L
L
H
H
H
X
X
NC
z
Hold
L
H
H
X
X
NC
NC
H
H
L
L
i
L
Z
Load
H
H
L
H
i
H
z
L
H
L
L
\
L
L
L
H
L
H
\
H
H
I = LOW-to-HIGH transition
NC = No Change from the previous state,
H =HIGH
L = LOW,
Z = High Impedance
Int. = Internal
For the 821 , the Hi-Z and Load functions only apply as the ER and CLE are not present in these devices.
For the 825, there are 3 output enables, and the composite output enable is asserted only
when all the three are LOW. If any one of the three output enables are HIGH, the output is disabled.
QUALITY SEMICONDUCTOR INC. 4-199
QSFCT821/3/5T, 2821 /3/5T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
CAPACITANCE
TA = 25°C, f = 1 MHz,Vin = 0V, Vout = 0V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,3-11,13
4
4
5
7
PF
15-22
6
6
7
9
PF
2,14,23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
-
4-200
QUALITY SEMICONDUCTOR INC.
QSFCT821/3/5T, 2821/3/5T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
-
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
-
0.2
I ii|
Iwl
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
HA
|te|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
rO 1 AAA
Vcc = MAX,Vo = GND(2,3)
-60
-
-
mA
lor
Current Drive
iLp 1 tAAA
Vcc = Min, Vo =2.0V
50
-
-
mA
Vic
Input Clamp Voltage
Vcc=MIN, lin = 18mA (3)
-0.7
-1.2
Volts
von
ft. ,lna .1 1 J 1 0 1 1
Output HiCaH voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 15 mA (MIL)
2.4
\ In It ^
volts
loh = 24 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
a
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc=5.0V and T^=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-201
QSFCT821/3/5T, 2821 /3/5T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 .5
mA
AlOC
Supply Current per
Vcc = MAX, Vin =3.4V, freq = 0 (2)
2.0
Input @TTL HIGH
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
0.25
mA/
Qccd
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data input pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
4-202
QUALITY SEMICONDUCTOR INC.
QSFCT821/3/5T, 2821 /3/5T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Sy
mbol
Description
Notes
(1 )
821A
823A
825A
2821A
2823A
282SA
821 B
823B
825B
2821 B
2823B
2825B
821C
823C
825C
821 D
823D
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
Clock to Y Delay
Com
10.0
7.5
6.0
5.3
ns
tP
OE-bw, FCT821/3/5
Mil
11.5
8.5
7.0
Com
2,3
20.0
15.0
12.5
12.5
Mil
2,3
20.0
16.0
13.5
Clock to Y Delay
OE=low, FCT2821/3/5
Com
10.0
7.5
Mil
11.5
8.5
Com
2,3
20.0
15.0
Mil
2,3
20.0
16.0
t
s
Data to Cp Setup Time
Com
4.0
3.0
3.0
3.0
Mil
4.0
3.0
3.0
t H
Data to Cp Hold Time
Com
2.0
1.5
1.5
1.5
Mil
2.0
1.5
1.5
tE
NS
EN to Cp Setup Time
Com
4.0
3.0
3.0
3.0
Mil
4.0
3.0
3.0
tENH
EN to Cp Hold Time
Com
2.0
0.0
0.0
0.0
2.0
0.0
0.0
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) Cload. 300 pF
4) Cbad=5pF
1
QUALITY SEMICONDUCTOR INC. 4-203
QSFCT821/3/5T, 2821 /3/5T
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Cload = 50 pF, Rload - 500Q unless otherwise noted
Symbol
Description
Notes
821A
823A
821B
823B
821C
r
821D
(1)
825A
2821 A
2823A
2825A
825B
2821 B
2823B
2825B
823C
825C
823D
Min
Max
Min
Max
Min
Max
Min
Max
tCLR
CLR to Y Delay 823/5
Com
11.0
9.0
8.0
7.0
Mil
12.0
9.5
8.5
CLR to Y Delay 2823/5
Com
11.0
9
Mil
12.0
9.5
tREC
CLR to Cp Setup Time
Com
6.0
6.0
6.0
6.0
Mil
7.0
6.0
6.0
tPWH
tPWL
Clock Pulse Width
High or Low
Com
2
7.0
6.0
6.0
6.0
Mil
2
7.0
6.0
6.0
tPZH
tPZL
Output Enable Time
OEtoYi FCT821-5
Com
12.0
8.0
7.0
6.5
Mil
13.0
9.0
8.0
Com
0 1
c.,o
23
15
12.5
12.5
■
Mil
2,3
25
16
13.5
Output Enable Time
OEtoYi, FCT2821 -5
Com
12
8.0
Mil
13
9.0
Com
2,3
23
Mil
2,3
25
tPHZ
Output Disable Time
OE to Yi
Com
2,4
7
6.5
6.2
6.2
tPLZ
Mil
6.2
2,4
8
7
Com
2
9
7.5
6.5
6.5
Mil
2
10
8
6.5
Unit
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not t
3) Cload. 300 pF
4) Cload -5 pF
4-204
QUALITY SEMICONDUCTOR INC.
s
-
QSFCT827T, 828T, 2827T, 2828T
Q
High Speed CMOS
Bus Interface
10-bit Buffers
■
QS54/74FCT827T
QS54/74FCT828T
QS54/74FCT2827T
QS54/74FCT2828T
—
FEATURES/BENEFITS
• Pin and function compatible to the 74F827/8
74FCT827/8 and 74FCT827T/8T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3.5V
Military product compliant to MIL-STD-883
FCT-T 827T/8T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• Std, A, and C speed grades with 4.4ns tPD for C • StdandA
• lol = 48mA Com., 32 mA Mil. • lol = 12m/>
2827T/8T
Built-in 25C2 series resistor outputs
reflection and other system noise
> with 5.0ns t
12mA Com.
DESCRIPTION
The QSFCT827T/828T and QSFCT827T/828T are 10-bit buffers/line drivers with three-state outputs
that are ideal for driving high-capacitance loads as in memory address and data buses. The 2827/8 are
25Q resistor output versions useful for driving transmission lines and reducing system noise. The 2827
series parts can replace the 827 series to reduce noise in an existing design. All inputs have clamp
diodes for undershoot noise suppression. All outputs have ground bounce suppression (see QSI
Application Note AN-001), and outputs will not load an active bus when Vcc is removed from the device.
=
FUNCTIONAL BLOCK DIAGRAM
FCT827
FCT828
=
QUALITY SEMICONDUCTOR INC.
QSFCT827T, 828T, 2827T, 2828T
PINOUTS
PDIP, SOIC, QSOP
25 C
T Y2
24 C
T Y3
23 C
T Y4
22 C
LNC
21 C
I Y5
20 C
1 Y6
19 C
T Y7
/
CO 0> Q
Q Q "
O (V ■*
Q Q Q
O
CO CO Z
Q Q O
? s u) n
>>->->
O
> 2
LJ o KM u> OJ
5 s g * >
CO O CM ■<
ZIP
t- CO
81
»- co in t-~
^ *W \J ^ ^
*~ t— CM
ALL PINS TOP VIEW
UJ Q Q Q Q Q !
ft > > > >• >-
FUNCTION TABLE
Inputs
Outputs
Function
fY-l>/VV
827
828
SET
SE2
Dl
Yl
Yl
L
L
L
L
H
Enabled
L
L
H
H
L
Enabled
H
Z
Z
HighZ
H
Z
Z
HighZ
H-High, L-Low, Z-High Impedance
4-206
QUALITY SEMICONDUCTOR INC.
QSFCT827T, 828T, 2827T, 2828T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage Vq -0.5V to 7.0V
DC Input Voltage V, -0.5V to 7.0V
AC Input Voltage (tor a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
1-11,13-23
SOIC
QSOP
PDIP.LCC
Note: Capacitance is characterized but not tested
ZIP
10 pF
Unit
PF
QUALITY SEMICONDUCTOR INC.
4-207
QSFCT827T, 828T, 2827T, 2828T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, Vcc=50V±5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
Test Conditions
Mln
Typ
(1)
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh-Vthl for All Inputs
0.2
| ft |
|lil|
Input Current
Input HIGH or LOW
Vcc= MAX
0 < Vin < Vcc
-
-
5
uA
|te|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
-
-
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND (2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN, lin = 18 mA (3)
-
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX & FCT2XXX
Vcc = MIN
loh = 15 mA (MIL)
2.4
Volts
loh = 24 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
loU 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
k)l = 12 mA (MIL)
0.50
lol=12mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
loU 12 mA (MIL)
21
28
38
a
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqc»5.0V and TA=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
4-208
QUALITY SEMICONDUCTOR INC.
QSFCT827T, 828T, 2827T, 2828T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
UUlcawcllt runcl
Supply Current
Vrr — MAY fren — n
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1 .9
m A
r
Supply Current per
Input @TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi -3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
=
INC.
4-209
QSFCT827T, 828T, 2827T, 2828T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA-0°C to 70°C, Vcc^.OViSyo Military TA=-55°C to 1 25°C, Vcc^.OVll 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Note
8
. 111
827/8A,
2827/8A
827/8B,
2827/8B
827/8C
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Ai to Yi, FCT827
Com
-
8
-
5
-
4.4
Mil
-
9
-
6.5
-
5.0
Com
2,3
-
15
-
13
-
10
Mil
2,3
-
17
-
14
11
Propagation Delay
Com
-
8
-
5
-
Ai to Yi, FCT2827
'■-Jii ,.; '..
Mil
-
9
-
6.5
-
Com
2,3
-
17
-
-
Mil
2,3
-
18
-
-
Propagation Delay
Ai to Yi, FCT828
Com
-
7.5
-
5
-
4.4
Mil
-
9.5
-
6.5
-
5.0
Com
2,3
-
14
-
13
-
10
Mil
2,3
-
16
-
14
-
11
Propagation Delay
Ai to Yi, FCT2828
Com
-
7.5
-
5
-
Mil
-
9.5
-
6.5
-
Com
2,3
-
17
-
-
Mil
2,3
-
18
-
-
tPZH
tPZL
Output Enable Time
OE to Yi, FCT827/8
Com
-
12
-
8
-
7
Mil
-
13
-
9
-
8
Com
2,3
-
23
-
15
-
14
Mil
2,3
25
16
15
Output Enable Time
OEtoYi, FCT2827/8
Com
12
8
Mil
13
9
Com
2,3
23
Mil
2,3
25
tPHZ
tPLZ
Output Disable Time
OEtoYi
Com
2
9
6
5.7
Mil
2
10
7
6.7
Com
2
10
7
6
Mil
2
10
8
7
Unit
Notes: 1. Minimum propagation delay values guaranteed but not tested.
2. This parameter is guaranteed but not tested.
3. Cload - 300 pF
4-210
QUALITY SEMICONDUCTOR INC.
QSFCT833T, 853T, 2833T, 2853T
Q
QS29FCT833T
High Speed CMOS qs29fct853t
Transceivers
iVrsth D^ksTw QS29FCT2833T
With Parity QS29fct2853t
=
=
ADVANCE INFORMATION
FEATURES/BENEFITS
• Pin and function compatible to the Am29833/53
• Parity generation and detection
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
TTL compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3 .5V
Military product compliant to MIL-STD-883
FCT 833T/53T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• lol = 48 mA Com., 32 mA Mil.
FCT 21
• Built-in 25Q series resistor outputs
reflection and other system noise
• lol = 12 mA Com.
ce
DESCRIPTION
The QSFCT833T/853T and QSFCT2833T/2853T are 8-bit high-speed CMOS TTL compatible
transceivers registers with three-state outputs and parity generate/detect logic that are ideal for driving
high capacitance loads such as memory and address buses. These parts generate and check odd
parity. All lows (zeros) in generates a one for parity. The 833 has a FF and the 853 has a latch to record a
parity error defined as a difference between parity generated from the inputs and the parity bit supplied
with the inputs. Once the FF/latch is set, it remains set until cleared by a pulse on CUR. ERR is the
output from this FF/latch and is open drain allowing multiple devices to be ORed. The 2833/53 devices
are 25Q resistor output versions useful for driving transmission lines and reducing system noise. The
2833 series parts can replace the 833 series to reduce noise in an existing design. All inputs have clamp
diodes for undershoot noise suppression. All outputs have ground bounce suppression (see QSI
Application Note AN-001), and outputs will not load an active bus when Vcc is removed from the device.
-
FUNCTIONAL BLOCK DIAGRAM
, Resistors in FCT2xxx only
R0-7
OFT
OER
CLK/ EfJ
CCR
TO-7
Parity
Gen
Error
FF/Latch
(833/853)
->• PARITY
->• ERR
i
QUALITY
INC.
4-211
FCT833/853 PIN CONFIGURATIONS
PDIP, SOIC, QSOP
te: Pin 13 (pin 16of LCC) is CLK
on 833 and EN on 853.
OER
R1
R3 (
R5
R7 (
CCR (
CLK/ER (
OET <
T6 (
T4 (
T2 (
TO ( 23
N
13
2
)
R0
4
)
R2
6
)
R4
8
)
R6
10
)
ERR
12
)
GND
14
)
OET
16
)
T7
18
)
T5
20
)
T3
22
)
T1
24
)
VCC
PIN DESCRIPTIONS
All packages are shown with the Top View
Name
I/O
Function
Ri
I/O
Data Bus, R side
Ti
I/O
Data Bus, T side
:
OET
Enable R to T
OER
Enable T to R
CLK
Parity FF Clock (833)
EN"
Parity Latch Enable (853)
CCR
Parity FF/Latch Clear
PARITY
0
Parity
ERR
0
Parity Error (Open Drain)
to I
TO
1
24 [J
T3
23 C
T4
22 IZ
NC
21 Q
T5
20 C
T6
19D
T7
4-212
QUALITY SEMICONDUCTOR INC.
QSFCT841/3/5T, 2841 /3/5T
Q
High Speed CMOS
Bus Interface
8, 9 & 10-bit
QS54/74FCT841T
QS54/74FCT843T
QS54/74FCT845T
QS54/74FCT2841T
QS54/74FCT2843T
QS54/74FCT2845T
FEATURES/BENEFITS
Pin and function compatible to the Am29841/3/5
74FCT 841/3/5 and 74FCT841 T/3T/5T
CMOS power levels: <7.5 mW static
Available in PDIP, ZIP, SOIC, QSOP, CERDIP
Undershoot Clamp diodes on all inputs
FCT-T 841 T,
JEDEC-FCT spec compatible
Fastest CMOS Logic family Available
A, B and C speed grades with 5.5ns tPD for C
lol = 48 mA Com, 32 mA Mil
• TTL-compatible input and output levels
• Ground bounce controlled outputs
• Reduced output swing of 0-3.5V
• Military product compliant to MIL-STD-883
FCT-T 2841 T, 2843T, 2845T
• Built-in 25Q series resistor outputs reduce
reflection and other system noise
• A, B and C speed grades with 5.5ns tPD for C
• lol = 12mA Com
DESCRIPTION
The QSFCT841T, 843T, and 845T are 10, 9, and 8-bit high-speed CMOS TTL-compatible buffered
latches with three-state outputs that are ideal for driving high capacitance loads such as memory and
address buses. The devices come in A, B, and C speed grades with 5.5ns (Max.) tPLH/tPHL for the C
grade. The 2841/3/5 devices are 25Q resistor output versions useful for driving transmission lines and
reducing system noise. The 284x eliminate the need for external series resistor in high speed systems
and can replace the 84x series to reduce noise in an existing design. All inputs have clamp diodes for
undershoot noise suppression. All outputs have ground bounce suppression , and outputs will not load
an active bus when Vcc is removed from the device.
=^=^========^=^=
FUNCTIONAL BLOCK DIAGRAM
Yi
only
QSFCT841/3/5T, 2841 /3/5T
PINOUTS
FCT841 PIN CONFIGURATIONS
INDE
t- o UJ
Q Q lO
1
24
□ vcc
DO C
2
23
□ YO
D1 C
3
Q.
o
22
□ Y1
D2 C
4
CO
21
□ Y2
D3 C
5
o
20
□ Y3
D4 C
6
d
19
□ Y4
D5 C
7
o
18
□ Y5
D6 C
8
(0
17
□ Y6
D7 C
9
qT
16
□ Y7
D8 C
10
5
15
□ Y8
D9 C
11
Q.
14
□ Y9
GND C
12
13
□ LE
D2 T
J 5
D3l
3 6
D4T
3 7
NCI
3 8
D5I
3 9
br.ub&fl r
D6I
3 1°
D7T
3 11
Q O
o eg Tf co oo Z o> r*- in co t- O
CN CO 00
y- co U5 r~» <
ZIP
S Ol LLI 00 CD tJ- CNJ p
Hi t- co m
5QQQQQ _,>>>>>
• ALL PINS TOP VIEW
CO C\l t—
Y2
Y3
I Y4
5 j o o ui ?
Q Q Z Z _l >-
C5
22 C
L NC
21 C
r Y5
20 C
L Y6
19C
L Y7
00
FCT841 LOGIC SYMBOL
PIN DESCRIPTIONS
FCT841
D
LE
Q
Di—/- D Q N / Y
10 I LE lUOlfT
LE
OE
"Yi
Name
Di
Yi
LE
OE
I/O
_
Function
Data Inputs
Data Outputs - Three State
Latch Enable
Output Enable
4-214
QUALITY SEMICONDUCTOR INC.
QSFCT841/3/5T, 2841/3/5T
FCT843 PIN CONFIGURATIONS
CO CM
D2 T
J 5
D3l
1 6
D4T
1 7
NCI
1 8
D5 I
3 9
D6 1
D7T
D 11
CM
8 S3 8
LCC
25 L
C Y2
24 C
L Y3
23 C
L Y4
22 n
Enc
21 C
L Y5
20 C
L Y6
L Y7
/
ITT I — I 11 UJ RJJ
UJ
o
<o co Z K f. m o ^ O
00 O CM •«
zip'
n »
-
Uj i- co in i>»
|0 Q Q Q Q
W CO CO J CM O
• ALL PINS TOP VIEW
PIN
DESCRIPTIONS
Name
I/O
Function
Di
1
Data Inputs
Yi
o
Data Outputs - Three State
OE
1
Output Enable
LE
1
Latch Enable
PRE
1
Preset
CUR
1
Asynchronous Reset
QUALITY SEMICONDUCTOR INC.
4-215
FCT845 PIN CONFIGURATIONS
O
fU r- (O Ul N Z J" (O^CMOU
IOQQOClOtC>->->->->
O W t
ZIP
»- co in
J S 5 U
n in n oj
QQQQp_i>>>->->-
6
• ALL PINS TOP VIEW
FCT845 LOGIC SYMBOL
Di.
8
LE
PRE —
FCT845
D Q
LE PRE CLR
— O —
CLR
GET
0E3
N1*
d y
PIN DESCRIPTIONS
Name
I/O
Function
Di
1
Data Inputs
Yi
0
Data Outputs - Three State
UFi
1
Output Enable
LE
1
Latch Enable
PRE
1
Preset
CUR
1
Asynchronous Reset
4-216
s
QSFCT841/3/5T, 2841 /3/5T
FUNCTION TABLES
QSFCT841, 2841
Inputs
Int.
O/P
Function
OE
LE
Dl
Ql
Yl
H
X
X
X
Z
Hi-Z
L
X
X
H
H
Output Enabled
L
X
X
L
L
Output Enabled
X
H
H
H
X
Transparent
X
H
L
L
X
Transparent
X
L
X
NC
X
Latched
QSFCT843/5, 2843/5
Innntc
Int.
O/P
Function
PRE
LE
Dl
Ql
Yl
H
H
H
X
X
X
Z
Hi-Z
X
X
L
X
X
H
H
Output Enabled
X
X
L
X
X
L
L
Output Enabled
H
H
L
H
H
H
H
Transparent
H
H
L
H
L
L
L
Transparent
H
H
L
L
X
NC
NC
Latched
H
L
L
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
Notes:
NC = No Change from the previous state
H = HIGH
L = LOW,
Z = High Impedance
Int. = Internal
QUALITY SEMICONDUCTOR INC. 4-217
QSFCT841/3/5T, 2841 /3/5T
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGstora9e Temperature
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Note: Capacitance is characterized but not tested
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
1,3-10,13
4
4
5
7
PF
15-22
6
6
7
9
PF
2,11,14,23
8
8
9
10
PF
QUALITY SEMICONDUCTOR INC.
===
-
QSFCT841/3/5T, 2841 /3/5T
i
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 125°C, VCC=5.0V±10%
Symbol
Parameter
Test Conditions
Mln
Typ
(D
Max
Unit
Logic HIGH for All Inputs
2.0
Vih
Input High Voltage
-
Volts
Vil
InDut LOW Voltaae
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh -Vthl for All Inputs
-
0.2
I lih I
| Nil |
I nil
innnt nurrpnt
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
5
uA
|bz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
5
los
Short Circuit Current
FCTXXX
Vcc = MAX, Vo = GND(2,3)
-60
mA
lor
Current Drive
FCT2XXX
Vcc = Min, Vo =2.0V
50
mA
Vic
Input Clamp Voltage
Vcc = MIN,lin = 18 mA (3)
-D 7
-1 9
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 15 mA (MIL)
2.4
Volts
loh = 24 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (250.)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
a.
lol = 12 mA (COM) I 24 I 28
I I
35
Notes : 1 . Typical values indicate Vcc=5.0V and Ta=25°C.
2. Not more than one output should be shorted and the duration is <1 second.
3. These parameters are guaranteed by design but not tested.
QUALITY SEMICONDUCTOR INC.
4-219
QSFCT841/3/5T, 2841/3/5T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
SuddIv Currsnt
Vcc = MAX, freq = 0
0V<Vin<0.2V or Vcc-0.2V<Vin<Vcc
1.5
mA
Alec
Supply Current per
Input @TTL HIGH
Vcc = MAX, Vin =3.4 V, freq = 0 (2)
2.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mA/
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi«3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMICONDUCTOR INC.
QSFCT841/3/5T, 2841 /3/5T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 1 25°C, VCC=5.0V+1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Not ss
(1)
841 A
843A
845A
2841A
841B
843B
845B
2841 B
841C
843C
845C
2841 C
Unit
2843A
2845A
2843B
2845B
2843C
2845C
tPHL
tPLH
Data to Y Delay
OE=low, FCT841/3/5
Com
Q
9
u.o
O.O
ns
m i
Mil
I U
/ .O
D.O
Com
2,3
1o
1 Q
1J
1 Q
1J
■in
Mil
2,3
10
15
4 r-
l D
Data to Y Delay
OE=low, FCT2841/3/5
Com
D.O
7 ft
Mil
Mil
1 1
7 R
o.u
Com
2 3
CM
R R
o.o
I o
Mil
20
7.5
15
ts
Data to LE Setup Time
Com
2.5
2.5
2.5
Mil
2.5
2.5
2.5
tH
Data to LE Hold Time
Com
2.5
2.5
2.5
Mil
3
2.5
2.5
t LEY
LE to Y Delay
OE-tow, FCT841/3/5
Com
12
8
6.4
Mil
13
10.5
6.8
Com
2,3
16
15.5
15
Mil
2,3
20
18
16
LE to Y Delay
OE-low, FCT2841/3/5
Com
12
8
8
Mil
13
10.5
10.5
Com
2,3
16
15.5
15
Mil
2.3
20
18
16
l_ I
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) Cload- 300 pF
4) Cload -5pF
QUALITY SEMICONDUCTOR INC. 4-221
QSFCT841/3/5T, 2841/3/5T
Commercial TA=0°C to 70°C, VCC=5.0V±5% Military TA=-55°C to 125°C, VCC=5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Notes
(D
841 A
843A
845A
2841A
2843A
2845A
841 B
843B
845B
2841 B
2843B
2845B
841 C
843C
845C
2841C
2843C
2845C
Unit
tSLEC
tCLR
t PRE
tCLRR
tPRER
t LEH
tPREL
tPHZ
tPLZ
CLR to LE Setup Time
CLR, PRE to Y Delay
843/5
CLR, PRE to Y Delay
2843/5
CLR, PRE
Recovery Time
LE Pulse Width High
PRE, CLR
Pulse Width Low
Output Enable Time
OEtoYi, FCT841
Output Enable Time
OEtoYi,FCT2841
Output Disable Time
OE to Yi
Com
Mil
Com
MM
Com
Mil
Com
Mil
Com
Mil
Com
Mil
Com
Mil
Com
2,3
Mil
2,3
Com
Mil
Com
2,3
Mil
2,3
Com
2,4
MM
2,4
Com
Mil
2.5
2.5
12
14
12
14
14
17
12
14
23
25
12
14
23
25
10
10
10
10
8.5
14
15
8.5
8.5
10
2.5
2.5
8.5
14
15
8.5
8.5
6.5
7.5
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) Cload = 300 pF
4) Cbad = 5pF
QUALITY SEMICONDUCTOR INC.
QSFCT861/2/3/4T, 2861/2/3/4T
Q
High Speed CMOS
Bus Interface
9 & 10-bit
Transceivers
•
QS54/74FCT861T
QS54/74FCT862T
QS54/74FCT863T
QS54/74FCT864T
QS54/74FCT2861T
QS54/74FCT2862T
QS54/74FCT2863T
QS54/74FCT2864T
FEATURES/BENEFITS
• Pin and function compatible to the 74F861/2/3/4
74FCT861/2/3/4 and 74FCT861T/2T/3T/4T
• CMOS power levels: <7.5 mW static
• Available in PDIP, ZIP, SOIC, QSOP, CERDIP
• Undershoot clamp diodes on all inputs
FCT-T861T/2T/3T/4T
• JEDEC-FCT spec compatible
• Fastest CMOS logic family available
• A and B speed grades with 6ns tPD for B
• lol = 48 mA Com., 32 mA Mil.
TTL-compatible input and output levels
Ground bounce controlled outputs
Reduced output swing of 0-3 .5V
Military product compliant to MIL-STD-883
FCT-T 2861T/2T/3T/4T
• Built-in 25£2 series resistor outputs reduce
reflection and other system noise
• Std and A speed grades with 8ns tPD for A
• lol = 12mA Com.
DESCRIPTION
The QSFCT861 -4T and QSFCT2861-4T are 9-bit and 1 0-bit inverting and non-inverting bus transceivers.
Separate enables for each bus control the direction of data flow. The 2861 -4A/B are 25J1 resistor output
versions useful for driving transmission lines and reducing system noise. The 2861 parts can replace the
861 series to reduce noise in an in existing design. All inputs have clamp diode for undershoot noise
suppression. All outputs have ground bounce suppression (see QSI Application Note AN-001), and
outputs will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAMS
QUALITY SEMICONDUCTOR INC.
4-223
QSFCT861/2/3/4T, 2861/2/3/4T
PINOUTS
OEE/UERT C
RO C
PDIP, SOIC, QSOP
ZIP
fcc
t- n in s
tr oc cc dc
KM
CC
EC
to •*
<M O
-
ALL PINS TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE
H=High, L=Low, Hi-Z-High Impedance
Pin Name
I/O
Description
Enables
861/3
862/4
Function
Ti
I/O
TBus
O'ER"
OET
TI
RI
TI
RI
Ri
I/O
R Bus
H
H
Z
Z
Z
Z
Disable, HI Z
0ER,"DET
I
R, T Enable
L
H
L
L
L
H
T->R
L
H
H
H
H
L
T->R
H
L
L
L
H
L
R->T
H
L
H
H
L
H
R->T
4-224
QUALITY
:tor INC.
QSFCT861/2/3/4T, 2861/2/3/4T
1
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Output Voltage V0 -0.5V to 7.0V
DC Input Voltage V| -0.5V to 7.0V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V(<0 -20 mA
DC Output Diode Current with Vq <0 -50 mA
DC Output Current Max. sink current/pin 120 mA
N=Number of Outputs, M=Number of inputs
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature -65° to +1 65°C
CAPACITANCE
TA = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0 V
Pins
SOIC
QSOP
PDIP.LCC
ZIP
Unit
4
4
5
7
pF
6
6
7
9
PF
1-11,13-23
8
8
9
10
PF
Note: Capacitance is characterized but not tested
QUALITY SEMICONDUCTOR INC.
4-225
QSFCT861/2/3/4T, 2861/2/3/4T
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
i
Commercial TA=0°C to 70°C, Vcc=5.0V+5% Military TA=-55°C to 1 25°C, VCC=5.0V±1 0%
Symbol
Parameter
N
Test Conditions
Min
Typ
(D
Max
Unit
Vih
Input High Voltage
Logic HIGH for All Inputs
2.0
Volts
Vil
Input LOW Voltage
Logic LOW for All Inputs
0.8
AVt
Input Hysterisis
Vtlh - Vthl for All Inputs
0.2
| tt|
I a I
Input Current
Input HIGH or LOW
Vcc = MAX
0 < Vin < Vcc
_
5
uA
|bz|
Off State Output
Current (Hi-Z)
Vcc = MAX,0<Vin<Vcc
_
_
5
los
01 iui i vyi I l uuiiciii
Vcc = MAX, Vo = GND (2,3)
-60
mA
FCTXXX
Inr
OUIICI 11 ulivc
Vcc = Min, Vo =2.0V
in
mA
FCT2XXX
Vic
Input Clamp Voltage
Vcc = MIN,lin= 18 mA (3)
«' ■
-0.7
-1.2
Volts
Voh
Output HIGH Voltage
FCTXXX &FCT2XXX
Vcc = MIN
loh = 15 mA (MIL)
2.4
Volts
loh = 24 mA (COM)
2.4
Vol
Output LOW Voltage
FCTXXX
Vcc = MIN
lol = 32 mA (MIL)
0.50
lol = 48 mA (COM)
0.50
Output LOW Voltage
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
0.50
lol = 12 mA (COM)
0.50
Rout
Output Resistance
FCT2XXX (25Q)
Vcc = MIN
lol = 12 mA (MIL)
21
28
38
SI
lol = 12 mA (COM)
24
28
35
Notes:
1 . Typical values indicate Vqq=5.0V and T^=25°C.
2. Not more than one output should be shorted and the
3. These parameters are guaranteed by design but not
duration is <1 second,
tested.
4-226 QUALITY SEMICONDUCTOR
QSFCT861/2/3/4T, 2861/2/3/4T
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, freq = 0
0V<Vin<;0.2V or Vcc-0.2V<;Vin<Vcc
1.5
mA
AlCC
Supply Current per
Input @ TTL HIGH
Vcc = MAX,Vin=3.4V,freq = 0 (2)
2
.0
Qccd
Supply Current per
input per mHz
Vcc = MAX, Outputs open and enabled
One bit toggling @ 50% duty cycle
Other inputs at GND or Vcc (3,4)
0.25
mAJ
MHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi=3.4V)
3. For flipflops Qccd is measured by switching one of the data in pins so that the output changes every
clock cycle. This is a measurement of device power consumption only and does not include power to
drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested.
4. Ic can be computed using the above parameters as explained in the Technical Overview section.
QUALITY SEMICONDUCTOR INC.
4-227
QSFCT861/2/3/4T, 2861/2/3/4T
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial: Ta = 0 °C to 70 °C, Vcc = 5.0V ±5% Military: Ta = -55°Cto+125°C, Vcc = 5.0V±10%
Cload = 50 pF, Rload = 500Q unlesss otherwise noted.
Symbol
Description
Notes
(1)
861-4A, 2861-4A
861 -4B, 2861 -4B
Unit
Com
Mil
Com
MM
Min
Max
Min
Max
Min
Max
Min
Max
tPHL
tPLH
Propagation Delay
Tlto/fm Ri, FCT861/3
-
8
-
9
-
6
-
6.5
ns
2,3
15
-
17
-
13
14
Propagation Delay
Ti to/fm Ri, FCT2861/3
,r.T ,)
8
-
9
-
6
■ i
6.5
2.3
-
17
-
18
-
-
.•«. 1
Propagation Delay
Ti to/fm Ri, FCT862/4
-
9
5.5
6.5
2,3
14
16
13
14
Propagatbn Delay
Ti to/fm Ri, FCT2862/4
9
10
5.5
6.5
2.3
17
18
tPZH
tPZL
Output Enable Time
OEtoTiorRi,FCT861-4
12
13
8
9
2,3
20
22
15
16
Output Enable Time
OEtoTiorRi,FCT2861-4
12
13
8
9
2,3
20
22
tPHZ
tPLZ
Output Disable Time
OEtoTiorRi
2,4
9
9
6
7
2
10
10
7
8
1. Minimum are guaranteed but not tested on propagation delays.
2. These parameters are guaranteed but not tested in final production.
3. Cload- 300 pF
4. Cload = 5 pF
4-228
QUALITY SEMICONDUCTOR INC.
General Information 1
Static RAM Products 2
FIFO Memory Products 3
FCT-T Logic Products 4
Application Notes 6
Quality And Reliability 7
Package Information 8
Sales Offices 9
-
QUALITY SEMICONDUCTOR INC.
QUALITY SEMICONDUCTOR INC.
QuickSwitch Table of Contents
;============= ======
QUICKSWITCH DATA SHEETS
Page
QuickSwitch Ordering Information 5-3
QuickSwitch Test Configuration 5-4
QuicSwitch Family Characteristics 5-5
QST3383/53 QuickSwitch Bus Exchange 5-17
QST3384/54 QuickSwitch Bus Connect 5-23
QUALITY SEMICONDUCTOR INC. 5-1
QuickSwitch Table of Contents
===== ==^==
■
■
QUALITY SEMICONDUCTOR INC.
QuickSwitch Ordering Information
QSXXQST XXXX XX X
Las
I
-\ Processing
H Package type
1 Device type
54 Military
74 Commercial
Processing:
Blank - Standard
B - MIL-STD 883
Package Type:
P - Plastic DIP, 300 mi
D - Ceramic DIP, 300 mil
L - Leadless Ceramic Chip Carrier
50 - Small Outline IC, 300 mil
51 - Small Outline IC, 150 mil
Z - Plastic ZIP
Q - QSOP, Quarter Size Outline Package, 150 mil
QUALITY SEMOCONDUCTOR INC.
5-3
QuickSwitch Test Configuration
Vcc
1
500 ft
r^\/\, O O— O 7.0V
Parameter
Tested
Switch
Position
t PLZ, t Pa-
Closed
All Others
Open
50£1 Coax to
Note: For detailed testing conditions and circuitry see QuickSwitch Family Characteristics
■
5-4
QUALITY SEMICONDUCTOR INC.
QuickSwitch Family Characteristics
QuickSwitch™ Family Circuit Characteristics
QuickSwitch™ Family Characteristics
The QuickSwitch™ family of CMOS Bus Switches introduced by QSI in 1990 by Quality Semiconductor
are high speed TTL bus connect devices. When they are enabled, the bus switches directly connect two
buses with a connection resistance of less than 5Q. They are like a 5 nanosecond multi-pole relay for TTL
signals with an on resistance of 5Q. Since these devices directly connect the bus signals they introduce
no additional propagation delay, timing skew or noise, are inherently bidirectional and dissipate no
additional power. They can replace traditional TTL buffers and transceivers to reduce propagation delay,
noise, control complexity and power. Applications of the QuickSwitch™ are discussed in application note
AN09.
QuickSwitch™ Circuitry
■
The basic element of the QuickSwitch™ is a fast, low on resistance, low capacitance, high current capacity
switch. The combination of low on resistance and low capacitance is provided by the QCMOS™ short
channel length, high performance CMOS process. Each switch consists of an N channel MOS transistor
driven by a CMOS gate, as shown beli
5Q when On
a O LJ O b
Off /On" O —
0/+5
QglckSwItch™ Blpck Diagram
When the switch in enabled, the gate of the N channel transistor is at Vcc (+5 volts) and the device is on,
with a typical on resistance of 5 ohms. When disabled, the switch is off. Due to the structure of the N
channel transistor, there is no direct leakage and very capacitance across the transistor in the off state. Off
state leakage is in the form of diode leakage to the substrate (ground) and is typically 1 nanoampere at
room temperature. Off state capacitance across the switch itself is small because the input and output
pins are shielded to some degree by the gate, which is grounded.
QUALITY SEMICONDUCTOR INC. 5-5
QuickSwitch Family Characteristics
QuickSwltch™ On Resistance
These devices have an on resistance of less than 5Q for voltages near ground and will drive in excess of
64 mA each. The resistance rises somewhat as the I/O voltage rises from a TTL low of 0.0 volts to a TTL
high of 2.4 volts. In this region the A and B pins are solidly connected, and the bus switch is specified in
the same manner as a TTL device over this range. This is shown in the on resistance plot below. As the
I/O voltage rises to approximately 4.0 volts, the transistor turns off. This corresponds to a typical TTL high
of 3.5 to 4.0 volts.
The input range also extends to 0.5 volts below ground. Below this voltage, the input clamp diode starts
to draw current. Also, the switch will start to turn on at voltages below approximately 0.8 volts, causing
leakage between the input and output. This negative signal capability allows video signals of up to 1 .0
volt peak to peak around ground to be switched.
On Resistance vs Vln @ 4.75 Vcc
1 6
1 4
1 2
1 0
Ron, a 8
6
4
2
0
-0.5 0 0.5 1 1.5 2
Vln, Volts
QuickSwltch™ On Resistance vs Vln
2.5
QUALITY SEMICONDUCTOR INC.
QuickSwitch Family Characteristics
QuickSwitch™ Vout versus Yin
The QuickSwitch™ provides a low resistance connection between inputs and outputs for voltages below
3.0 volts. As the I/O voltage rises above 3 volts, the resistance increases until the switch turns off, at
approximately 4.0 volts. This is shown in the Vout versus Vin charts. The switch on resistance is
determined by the lower of the voltages on the two I/O pins. The resistance rises as the I/O voltage rises,
as shown below.
Vout vs Vln for Various Loads, Typical
4.5
4.0
3.5
3.0
2.5
Vout 2.0
1.5
1.0
0.5
0.0
-0.5
i ....
r*i_i —
■ 1 KU
□ 10Kfl
— ♦ — 10 Megn
-1.0 0.0 1.0
2.0 3.0 4.0 5.0
Vln, Volts
Voltage Drop vs Vln for Various Loads, Typical
0.50
0.45
0.40
0.35
0.30
AV 0.25
0.20
0.15
0.10
0.05
-I
m p
■ u ■
f J
■■■1 d
-0.5 0.0 0.5 1.
1.5 2.0 2.5 3.0 3.5 4.0
Vln, Volts
QuickSwitch™ Vout vs Vln
QUALITY SEMICONDUCTOR INC. 5-7
QuickSwitch Family Characteristics
QuickSwitch™ Vout versus Vcc
The QuickSwitch™ output voltage for an input voltage equal to Vcc is approximately 1 .0 to 1 .5 volts below
Vcc. Increasing or decreasing Vcc will increase or decrease the output voltage by the same amount, as
shown in the plot below. In this plot, the "AV" curves shown the difference between the output and Vcc,
i.e. the voltage drop across the switch.
The output limit of 1 .0 to 1 .5 volts below Vcc is because an N channel transistor is used as the switch
which turns off as its gate to source voltage falls below this value. A single N channel device is used
rather than an N channel and P channel combination so that the switch can be powered down and not load
either the input or the output. If a P channel device is used, it, by nature, provides a clamp diode to Vcc
which will load the A or B inputs when Vcc is removed.
■ 10 Meg
□ 10K
• AV@10 Meg
0 AV@10K
3.0
3.5
4.0
Vcc
4.5 5.0
QuickSwitch™ Vout and Voltage Drop versus Vcc at Vin = Vcc
5-8
QUALITY SEMICONDUCTOR INC.
■
QuickSwitch Family Characteristics
QuickSwitch™ Operation with TTL Signals
The QuickSwitch™ provides a path for a driving device to drive capacitance to ground and to drive
capacitance up from ground. This is shown below. When the A (or B) input is driven to a TTL low of 0.0
volts, the N channel transistor is fully on and the B (or A) output will follow it. Likewise, when the A (or B)
input is driven from a TTL low of 0.0 volts to a TTL high, the capacitor side of the N channel switch is at 0.0
volts, the switch is fully on and the B (or A) output will follow it through threshold and beyond. This means
that the rise and fall time characteristics and waveforms of the B (or A) output will be determined by the TTL
driver, not the bus switch. The switch introduces no propagation delay, to a first approximation.
TTL High to Low Transition
TTL Driver
74FCT244C, etc
T
+5
Load
Capacitance
TTL Low to High Transition
0 => 3.5V
TTL Driver
74FCT244C, etc
QuickSwitch™ Bus Switch Operation
When the QuickSwitch™ is disabled, the N channel transistor gate is at 0.0 volts, and the transistor is off.
By the nature of the N Channel transistor design, the A and B pins are fully isolated when the transistor is
off. Leakage and capacitance is to the chip substrate (i.e., ground) rather than between input and output.
This minimizes feedthrough in the off state. Because only an N channel transistor is used, either A or B
pin(s) can be taken to Vcc and above, and the device can be powered down without loading either bus.
The bus switch can replace drivers and transceivers in systems if bus repowering is not required. Since
the bus switch directly connects two buses, it provides no drive of its own but relies on the device that is
driving data onto the connected buses. If the additional loading of the connected bus is small enough,
there is a net gain in speed. For example, the sensitivity to loading of a driver such as the 74FCT244 is
typically 2 ns/100 pF. If the connected bus adds 50 pF of loading the added delay will be 1 ns. This is
much less than the 4 to 10 ns delay of the buffer or transceiver the bus switch replaces.
QUALITY SEMICONDUCTOR INC.
5-9
QuickSwitch Family Characteristics
Input Clamp
Since the QuickSwitch™ is intended for high speed logic applications, it has input undershoot clamp
diodes. The input clamp diode turns on when the input goes negative, providing clamp action for
negative undershoot transients and thereby reducing system noise. Note that there is no positive clamp.
The input can go above Vcc without conducting current. In fact, actual input leakage is of the order of a
few nanoamperes over the input range of 0.0 to 5.0 volts at room temperature. Graphs of typical input
characteristics is shown below.
-3.5 I 1 1 1 L
•1 -0.75 -0.5 -0.25 0
Input Voltage, Volts
QST Input Characteristics
5-10
QUALITY SEMICONDUCTOR INC.
QuickSwitch Family Characteristics
Charge Infection at Turnoft
When a QuickSwitch™ connected to a capacitive load turns off, the capacitance holds the prior signal
level. This provides a hold function which is called a dynamic latch in digital terms or a track and hold in
analog terms. When the switch turns off, a small amount of charge is coupled from the switch gate to the
outputs. Since the gate transitions from high to low at turn off, this will couple a negative step into the
capacitive load. For a 50 pF bad, this step will be approximately 30 millivolts. The corresponds to a
charge injection of 1 .5 picocoulombs. A plot of charge injection versus Vin is shown below. To calculate
the negative voltage step at turn off, divide the charge injection value in picocoulombs by the capacitance
in picofarads.
The hold time for typical capacitances and leakages can be quite long compared to the clock cycle times of
fast systems. Assuming a 1 volt change in level and a typical total system leakage of 50 nanoamperes, the
hold time is of the order of (50 x 1 0E-12/50 x 1 0E-9) = 1 millisecond.
at Turnpff versus Vln
-
>
QUALITY SEMICONDUCTOR INC. 5-11
■
QuickSwitch Family Characteristics
Ratings, Specifications and Waveforms
General Comments
to provide
Absolute Maximum Ratings
The Absolute Maximum ratings define the limits of operation of the QST devices. Operation beyond
these limits may cause permanent damage the device, i.e. it may no longer meet its specifications or may
even cease to function.
The Supply Voltage rating defines the absolute maximum Vcc voltage that can be safely be applied to tie
device. The Supply Voltage rating of QST is consistent with the equivalent ratings of other TTL devices,
and system power distribution design must take these ratings into consideration for reliable operation.
The Supply Voltage rating is determined by the internal breakdown voltage ratings of the device. High
performance processes such as QCMOS™ strive to reduce device dimensions in order to increase
speed. Reducing device dimensions also tends to reduce breakdown voltages. If Vcc to the device is
taken too high, the internal device breakdown voltages may be exceeded, excessive current drawn, and
devices may be permanently damaged because of the high resulting power dissipation and heat
generated in the device. QST devices typically have breakdown voltages well above the Supply Voltage
rating listed, care must be taken that the Vcc supply does not go above this rating, even transiently.
The Input Voltage rating defines the maximum voltage that can be applied to an input, including the
switch pins. Note that this voltage is independent of Vcc, and the input can go above Vcc. The device
can be powered down and not load its inputs. This is because there is no output clamp diode to Vcc.
The AC Input Voltage rating is an undershoot specification. It states that undershoot pulses of up to -3
volts can be tolerated on any input pin including switch inputs without damage to the device. However,
large undershoot pulses can cause significant clamp current and the energy of these pulses is dissipated
in the device. If these pulses have a high duty cycle, the average power and the average current in the
undershoot pulses can be significant and must be taken into account to insure that the DC Input Diode
Current and the Maximum Power Dissipation ratings are not exceeded.
The DC Input Diode Current defines the rating of the input undershoot clamp diode. The average current
from undershoot clamp pulses must be below this rating.
The DC Switch Current Maximum Sink Per Pin defines the maximum DC switch current that can be drawn
per switch to pull down an external load to ground.
The Maximum Power Dissipation defines the maximum total power dissipation capability of the device. It
represents a package power dissipation limit for the device, above which the die will overheat and be
damaged. Note that the power dissipation limit includes power dissipated by the input clamp diodes as
well as power from Vcc for driving internal circuitry.
The Storage Temperature rating defines the maximum temperature that the packages may be subject to
for long term storage. Long term storage above this temperature may cause degradation of the chip. This
is a precautionary specification. Chips cannot be subjected to extremely high temperatures, significantly
above the Storage Temperature rating, even if unpowered and be expected to work reliably thereafter.
Input and Switch Capacitance
5-12
QUALITY SEMICONDUCTOR INC.
s
QuickSwitch Family Characteristics
Each input control pin and switch pin has a capacitance associated with it. The switch pins have two
capacitance values, one for the off state and one for the on state. In the off state, each switch pin is
isolated and has a capacitance to ground. In the on state, two pins are connected, and the capacitance
seen at one pin includes the capacitance of the other pin to which it is connected.
PC Electrical Characteristics
The DC Electrical Specifications define the input requirements for valid operation, output specifications
during valid operation and responses to applied signals such as leakage currents, clamp voltages and
output resistance.
Vih defines the minimum DC input voltage for a TTL high. This applies to the control input pins. Typical
TTL high voltages applied to inputs are 3.5 to 5.0 volts. VU defines the maximum DC input voltage for a
TTL low. This applies to the control input pins. Typical TTL low voltages applied to inputs are 0.0 to 0.5
volts. Note that the AC characteristics are guaranteed for input switching values of 3.0 volts for a TTL hii
and 0.0 volts for a TTL low.
AVt defines the typical input hysteresis. This applies to the control input pins. Input hysteresis is the
difference in input threshold voltages for low-to-high and high-to-low input transitions. This specification
guarantees that there is some hysteresis and gives its typical value.
Jib and Jil define the maximum input leakage current; ]qz defines the maximum switch off state leakage
current. The maximum input or switch leakage is ±1 uA and a typical value is 1 -5 nanoamperes at 25 °C.
los defines switch short circuit current for one input at Vcc and the other input at ground. This is an
indication of drive capability of the switch to pull up capacitance from ground.
Mfi defines the input undershoot clamp voltage for a specified input current. It guarantees that the input
undershoot clamp is sufficiently low impedance to provide useful clamping action.
Ron defines the range of resistance values for resistor devices. It is guaranteed over voltage and
temperature. This is an incremental resistance measured at the test current. The resistance is calculated
as ( Vout at 1 2 mA - Vout at 0 mA) divided by (1 2 mA - 0 mA).
QUALITY SEMICONDUCTOR INC. 5-13
QuickSwitch Family Characteristics
Recommended Operating Conditions
The DC Electrical Characteristics define the limits of operation for the device. The recommended
operating conditions are stated at the top of the DC Electrical Characteristics and Switching
Characteristics specifications. The recommended operating conditions are those the parts are expected
to encounter in normal operation. The switching characteristics are guaranteed under these conditions.
The recommended operating conditions conditions for QST logic cover operating temperatures of 0 to
70 °C for commercial and -55 to + 125 °C for military temperature range parts and a nominal Vcc voltage of
5.0 volts with an operating range of within ±1 0% of this value (i.e. 4.5 to 5.5 volts).
Switching Characteristics
Data Propagation Delay Specifications: t PLH. t PHL
Data propagation delay specifications through the switch are shown for reference only. Actual
propagation delay through the switch is very low, approximately the propagation delay of a 5 ohm resistor.
For a 50 pF load, this is equivalent to a propagation delay of 0.25 nanosecond.
Switch Turn Qn and Turn Off Delay Specifications; t PZH. t PZL t PHZ, t PLZ
Switch turn on and turn off delay specifications cover two conditions: going from the high impedance
(high-Z) condition to the low impedance, on state condition, and going from the low impedance, on state
condition to the high impedance (high-Z) condition. In the high-Z to low-Z case, propagation delay
measurements are done in the same manner as any other: the output must settle to the correct logic high
or low state before the stated maximum time, tPZH or t£ZL.
In the low-Z to high-Z case, the output must be in the high-Z condition by the stated maximum time, t PHZ
or t PLZ. Special measurement must be done to detect the high-Z condition. Since the high-Z condition
means the output is undriven, the high-Z condition is detected by using an external resistor load network
to drive the output away from the previous high or low logic state to a level determined by the load
network. The output will start to move to this level when the output has turned off. This is detected by a
change in the output level away from the previous high or low. The output is defined as being in the high-
Z state when the output moves from its prior high or low state by 300 millivolts. Note that this specification
is usually guaranteed by design, verified by device characterization and not tested in production.
Switch Selection Delay Specifications: t BX
Switch selection or multiplex delay specifications define the time required to turn off one set of switches
and turn on another set. It is measured from the transition of the control input to the switched output
changing state high or low.
5-14
===== =
QUALITY SEMICONDUCTOR INC.
QuickSwitch Family Characteristics
AC Test Conditions
AC test conditions are concerned with propagation delays at outputs relative to applied signals. QST is
tested using industry standard test signals. Input signals transition between levels of 0.0 volts for a logic
low to 3.0 volts for a logic high with a transition time of 2.5 nanoseconds measured from the 10% to 90%
points of the signal transition. Rise and fall times of 1 ns are used to test minimum pulse widths such as
clock width, t W.
AC Test Circuitry
The AC test circuitry is shown below. This test circuitry is an industry standard for QST logic and many
other high performance TTL logic families. Inputs under test are driven by a pulse generator with an
output impedance of 50 ohms. Outputs are loaded with 50 picofarads and 500 ohms to ground except for
three state tests. The 500 ohm resistor to ground is typically used as a part of a 10:1 probe for an
oscilloscope used to measure the output. The 10:1 probe consists of a 450 ohm resistor feeding into a
50 ohm coax cable to the oscilloscope. This provides a 10:1 probe with no appreciable capacitive loading
by the 450 ohm resistor. This is the preferred scheme for correlation to QSI test data.
Switch turn off testing of Tplz and Tpzl modifies the test load. An additional 500 ohm resistor is switched
to +7.0 volts for these tests. This biases the output to 3.5 volts for testing the transition from high-Z to a
TTL low and from a TTL low to high-Z. The 3.5 volts is an industry standard value chosen to represent the
realistic situation of transitioning to or from a potential TTL high at the output under high-Z conditions.
500 £1
-CTIm) 7.0V
Parameter
Tested
Switch
Position
tPLZ.tPZL
Closed
All Others
Open
50£1 Coax to
Oscilloscope
QST Test Circuit
The charge injection test circuitry is shown below. Charge injection is measured at turn off for for 0.0 volts
Vin with a 50 pF load. This results in a negative turn off step of 30 mV for 1 .5 pC charge injection.
10 Megohm, 10X
Oscilloscope Probe
=
QUALITY SEMICONDUCTOR INC.
5-15
QuickSwitch Family Characteristics
AC Test Waveforms
General waveforms are shown below for testing all input to output delays. Outputs are shown for normal
and inverted signal phases, as determined by the logic function being tested. Switch turn off test
waveforms are also shown, indicating the 300 millivolt change in level used to detect the high-Z condition.
3.0V
Input
Output In
Same
Phase
Control
Input
Output
Output In
—
Output
1.5V
tPHZ
NOTES: 1 . For t PZH the output goes from Hi-Z to a HIGH state, and the input is a control input
2. For t PZL the output goes from Hi-Z to a LOW state, and the input is a control input
3. For t PLZ the output goes from LOW to a Hi-Z state, and the input is a control input
4. For t PHZ the output goes from HIGH to a Hi-Z state, and the input is a control input
QST Test Waveforms
■
■
■
5-16
QUALITY SEMICONDUCTOR INC.
-
QST3383, QST3583
Q
High Speed CMOS
Bus Exchange
Switches
QS54/74QST3383
QS54/74QST3583
('3583 PRELIMINARY)
=
FEATURES/BENEFITS
• 5Q switches connect inputs to outputs
• Direct bus connection when switches on
• Zero propagation delay (3383)
• Undershoot Clamp diodes on all inputs
• Low power CMOS proprietary technology
—
3583 is 25Q version for low noise
Bus exchange allows nibble swap
Zero ground bounce in flow-through mode
TTL-compatible input and output levels
Available in 24-pin DIP, ZIP, SOIC and QSOP
DESCRIPTION
The QS54/74QST3383 and 3583 each provide two sets of ten high-speed CMOS TTL-compatible bus
switches. The low on resistance (5£2) of the 3383 allows inputs to be connected to outputs without
adding propagation delay and without generating additional ground bounce noise. The 3583 adds an
internal 25£l resistor to reduce reflection noise in high speed applications. The bus enable (BE) signal
turns the switches on. The bus exchange (BX) signal provides nibble swap of the AB and CD pairs of
signals. This exchange configuration allows byte swapping of buses in systems. It can also be used as a
quad 2-to-1 multiplexer and to create low delay barrel shifters, etc.
FUNCTIONAL BLOCK DIAGRAM
AO
BO
A4
B4
BX
BE
PIN DESCF
IPTION
Name
I/O
Function
AO-4, BO-4
I/O
Buses A, B
CO-4, DO-4
I/O
Buses C, D
BE
I
Bus Switch Enable
BX
I
Bus Exchange
FUNCTION TABLE
8=9
BE
BX
AO-4
BO-4
Function
H
X
Hi-Z
Hi-Z
Disconnect
L
L
CO-4
DO-4
Connect
L
H
DO-4
CO-4
Exchange
QUALITY SEMICONDUCTOR INC.
5-17
QST3383, QST3583
PIN CONFIGURATIONS
BE
CO
AO
BO
DO
C1
A1
B1
D1
C2
A2
GND C
c
c
c
c
c
c
c
c
c
c
c
1
2
3
4
5
6
7
8
9
10
11
12
Q.
o
CO
o
Q.
o
24
23
22
21
20
19
18
17
16
15
14
13
□ vcc
□ D4
□ B4
□ A4
□ C4
D3
B3
A3
C3
D2
B2
BX
BE C
AO C
DO C
A1
D1
A2 C
BX C
ALL PINS TOP VIEW
A3 (
D3 C
A4 C
D4 C
9 ±
N 10
11
13
15
17
19
21
23
12
14
16
18
20
22
24
) CO
) BO
) C2
) B1
) C2
) GND
) B2
) C3
) B3
)C4
) B4
) VCC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Switch Voltage Vs -0.5V to Vcc + 0.5V
DC Input Voltage V| -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Current Max. sink current/pin 120 mA
Maximum Power Dissipation 0.5 watts
TSTGs,ora9e Temperature -65° to +165°C
CAPACITANCE
Ta = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0V
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance, Controls
Vin = 0 V
6
pF
Coff
A/B I/O Capacitance, Switch Off
Vin = 0 V
6
pF
Con
A/B I/O Capacitance, Switch On
Vin = 0 V
10
PF
Capacitance is guaranteed but not tested
5-18
QUALITY SEMICONDUCTOR INC.
QST3383, QST3583
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2.0
Volts
Vih
Guaranteed Logic HIGH
for Control Inputs
""
-
Input LOW Voltage
I
0.8
Volts
Vil
Guaranteed Logic LOW
for Control Inputs
-
1 Tin |
Input Leakage Current
0 < Vin < Vcc
1
uA
|bz|
Off State Current (Hi-Z)
0 <, A, B < Vcc
.001
1
uA
|bs|
Short Circuit Current (2)
A (B) = OV, B (A) = Vcc
100
mA
Vic
Clamp Diode Voltage
Vcc = Min, lin = -18mA
-0.7
-1.2
Volts
Ron
Switch On Resistance
(Notes: 3,4)
Vcc = Min, Vin = 0.0 Volts
Ion = 48 mA
of
33XX
5
7
CI
35XX
24
28
35
Q
Vcc = Min, Vin = 2.4 Volts
Ion = 15 mA
33XX
10
15
a
35XX
24
35
48
Notes:
1 . Typical values indicate Vqq=5.0V and T^-25°C.
2. Not more than one output should be used to test this high power condition, and the duration is <1 second.
3. Measured by voltage drop between A and B pin at indicated current through the switch. On resistance is
determined by the lower of the voltages on the two (A B) pins.
4. 35xx Ron is a preliminary specification.
■
On Resistance vs Vin @ 4.75 Vcc (338X Only)
Ron, Ci
0.5 1.0
1.5 2.0
Vin, Volts
2.5
3.0
3.5
QUALITY SEMICONDUCTOR INC.
5-19
QST3383, QST3583
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Typ
Max
Unit
Ice
Quiescent Power
Supply Current
Vcc = MAX, Vi = GND or Vcc, f = 0
-
-
1.5
mA
AlCC
Pwr Supply Current,
per Input High (2)
Vcc = MAX, Input = 3.4 V,f = 0
Per control input
2.5
mA
Qccd
Dynamic Pwr Supply
Current per mHz (3)
Vcc = MAX, A & B pins open,
Control input toggling
0.25
mA/
mHz
@ 50% duty cycle
Ic
Total Power
Supply Current (4,5)
Vcc = MAX, A & B pins at 0.0V,
Control inputs toggling
@ 50% duty cycle
9.0
mA
Vih = 3.4V,fclock=10mHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V, control inputs only). A and B pins do not contribute to Ice.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance
at the specified frequency. The A and B inputs generate no significant AC or DC currents as they transition.
This parameter is not tested but is guaranteed by design.
4. Ic- I Quiescent + I Inputs* I Dynamic
lc=lcc+ AlccDhNt+ Qccd (filMi)
Ice- Quiescent Current
Alec- Power Supply Current for each TTL High input (Vi-3.4V, control inputs only)
Dh- Duty Cycle for each TTL input that is High (control inputs only).
Nt- Number of TTL inputs that are at DH (control inputs only).
fi= frequency that the inputs are toggled (control inputs only).
5. Note that activity on A and/or B inputs do not contribute to Ic if A and B inputs are between gnd and Vcc.
The switches merely connect and pass through activity on these pins. For example: If the control inputs are at
OV and the switches are on, Ic will be equal to Ice only regardless of activity on the A and B pins.
5-20
QUALITY SEMICONDUCTOR INC.
QST3383, QST3583
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50pF, Rload = 500Q unless otherwise noted
Symbol
Description
Note
Com
Mil
Unit
Mln
Max
Mln
Max
t PLH
tPHL
Data Propagation Delay
Ai to Bi, Bi to Ai
>WOA
2,3
U .c.0
0.25
ns
358X
2,3,7
1.25
1.25
ns
t PZH
t PZL
Switch Turn On Delay
BE to Ai, Bi
338X
1
1.5
6.5
1.5
7.5
ns
358X
1,7
1.5
7.5
1.5
8.5
ns
t PLZ
tPZL
Switch Turn Off Delay
BE to Ai, Bi
338X
1,2
1.5
5.5
1.5
6.5
ns
358X
1,2,7
tBX
Switch Multiplex Delay
BXtoAi.Bi
338X
1
1.5
6.5
1.5
7.5
ns
358X
1,7
1.5
7.5
1.5
8.5
ns
|C*|
Charge Injection, Typical
338X
4,6
1.5
1.5
pC
358X
4,6,7
I Odd |
Differential Charge
Injection, Typical
338X
5,6
<.5
<.5
PC
358X
5,6,7
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and
the load capacitance. The time constant for the switch and aba alone is of the order of 0.25 ns for 50 pf load.
Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little
propagation delay to the system. Propagatbn delay of the bus switch when used in a system is determined by
the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
4) Measured at switch turn off, A to C, load = 50 pF in parallel with 1 0 meg scope probe, Vin at A - 0.0 volts.
5) Measured at switch turn off through bus multiplex, A to C => A to D, B connected to C, load = 50 pF in parallel with
10 meg scope probe, Vin at A = 0.0 volts. Charge injection is reduced because the injection from the turn off of
the A to C switch is compensated by the turn on of the B to C switch.
6) Characterized parameter. Not 100% tested.
7) Preliminary data, subject to change.
QUALITY SEMICONDUCTOR INC.
5-21
QST3383, QST3583
■
5-22 QUALITY SEMICONDUCTOR INC.
QST3384, QST3584
Q
High Speed CMOS
10-bit Bus Switches
QS54/74QST3384
QS54/74QST3584
('3584 PRELIMINARY)
FEATURES/BENEFITS
• 5C1 switches connect inputs to outputs
• Direct bus connection when switches on
• Zero propagation delay (3384)
• Undershoot Clamp diodes on all inputs
• Low power CMOS proprietary technology
3584 is 25ft version for low noise
Two enables control 5 bits each
Zero ground bounce in flow-through mode
TTL-compatible input and output levels
Available in 24-pin PDIP, ZIP, SOIC and QSOP
DESCRIPTION
The QS54/74QST3384 and 3584 each provide a set of ten high-speed CMOS TTL-compatible bus
switches. The low on resistance (5Q) of the 3384 allows inputs to be connected to outputs without
adding propagation delay and without generating additional ground bounce noise. The 3583 adds an
internal 25ft resistor to reduce reflection noise in high speed applications. The bus enable (BE) signals
turn the switches on. Two bus enable signals are provided, one for each of the upper and lower five bits
of the two 10-bit buses.
FUNCTIONAL BLOCK DIAGRAM
AO
|
I
4
I
A4
A5
I
A9
BEA
BEB
BO
B4
■B5
■B9
PIN DESCR
IPTION
Name
I/O
—
Function
AO-9
I/O
Bus A
BO-9
I/O
Bus B
BEA7BEB
I
BEA"
BEB
BO-4
B5-9
Function
H
H
Hi-Z
Hi-Z
Disconnect
L
H
AO-4
Hi-Z
Connect
H
L
Hi-Z
A5-9
Connect
L
L
AO-4
A5-9
Connect
QUALITY SEMICONDUCTOR INC. 5-23
QST3384, QST3584
PIN CONFIGURATIONS
ALL PINS TOP VIEW
B1
1
2
) BO
3
4
)A1
5
6
> B2
7
Q.
8
) A3
9 r:
N
10
) B4
) GND
12
13
) A5
14
15
> B6
16
17
>A7
18
19
) B8
20
21
) A9
22
23
) vcc
24
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground -0.5V to +7.0V
DC Switch Voltage Vs -0.5V to Vcc + 0.5V
DC Input Voltage V( -0.5V to Vcc + 0.5V
AC Input Voltage (for a pulse width <20 ns) -3.0V
DC Input Diode Current with V|<0 -20 mA
DC Output Current Max. sink current/pin 120 mA
Maximum Power Dissipation 0.5 watts
TSTGStora9e Temperature -65° to +165°C
CAPACITANCE
Ta = 25 °C, f = 1 MHz, Vin = 0V, Vout = 0V
Name
Description
Conditions
Typ
Max
Unit
Cin
Input Capacitance, Controls
Vin = 0 V
6
pF
Coff
A/B I/O Capacitance, Switch Off
Vin = 0 V
6
pF
Con
A/B I/O Capacitance, Switch On
Vin = 0 V
10
PF
Capacitance is guaranteed but not tested
5-24
QUALITY SEMICONDUCTOR INC.
QST3384, QST3584
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
1 1
Symbol
Parameter
■ V ■ %M ill V * V ■
Test Conditions
Min
Typ
Max
Unit
Vih
InDut HIGH Voltaae
Guaranteed Logic HIGH
2.0
Volts
for Control Inputs
VII
Inrjut LOW Voltane
iii^ui v uuayo
Guaranteed Logic LOW
0.8
Volts
for Control Inputs
|lin|
Input Leakage Current
0<Vin<Vcc
1
uA
\toz\
Off State Current (Hi-Z)
0 < A, B < Vcc
.001
1
uA
Itosj
Short Circuit Current (2)
A (B) = 0V, B (A) = Vcc
100
mA
Vic
Clamp Diode Voltage
Vcc = Min, lin = -18mA
-0.7
-1.2
Volts
Ron
Switch On Resistance
(Notes: 3,4)
Vcc = Min, Vin = 0.0 Volts
Ion = 48 mA
33XX
5
7
Q
35XX
24
28
35
Q
■
Vcc = Min, Vin = 2.4 Volts
Ion = 15 mA
33XX
10
15
a
35XX
24
35
48
a
Notes:
1 . Typical values indicate Vcc«5.0V and T^=25°C.
2. Not more than one output should be used to test this high power condition, and the duration is <1 second.
3. Measured by voltage drop between A and B pin at indicated current through the switch. On resistance is
determined by the lower of the voltages on the two (A, B) pins.
4. 35xx Ron is a preliminary specification.
On Resistance vs Vin @ 4.75 Vcc (338X Only)
Ron, £2
16
14
12
10
8
6
4
2
0 •
0
0.5
1.0
1.5 2.0
Vin, Volts
2.5
3.0
3.5
QUALITY SEMICONDUCTOR INC.
5-25
QST3384, QST3584
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Mln
Typ
Max
Unit
Ice
Quiescent Power
Vcc = MAX, Vi = GNDorVcc,f = 0
-
-
1.5
mA
Supply Current
AlCC
Pwr Supply Current,
per Input High (2)
vec = MAX, input = 3.4 V, f = 0
mA
Per control input
Qccd
Dynamic Pwr Supply
Current per mHz (3)
Vcc = MAX, A & B pins open,
0.25
mA/
Control input toggling
@ 50% duty cycle
mHz
b
Total Power
Supply Current (4,5)
Vcc = MAX, A & B pins at 0.0V,
Control inputs toggling
9.0
mA
@ 50% duty cycle
Vih = 3.4V, f clock = 10 mHz
1 . For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
2. Per TTL driven input (Vi-3.4V, control inputs only). A and B pins do not contribute to Ice.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance
at the specified frequency. The A and B inputs generate no significant AC or DC currents as they transition.
This parameter is not tested but is guaranteed by design.
4. Ic« I Quiescent + I Inputs* I Dynamic
lc=lcc+ AlccDhNt-f Qccd (fiNi)
Ice- Quiescent Current
Alcc= Power Supply Current for each TTL High input (Vi-3.4V, control inputs only)
Dh= Duty Cycle for each TTL input that is High (control inputs only).
Nt= Number of TTL inputs that are at DH (control inputs only).
fi= frequency that the inputs are toggled (control inputs only).
5. Note that activity on A and/or B inputs do not contribute to Ic if A and B inputs are between gnd and Vcc.
The switches merely connect and pass through activity on these pins. For example: If the control inputs are at
0V and the switches are on, Ic will be equal to Ice only regardless of activity on the A and B pins.
j
5-26
QUALITY SEMICONDUCTOR INC.
QST3384, QST3584
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (338x only)
Commercial TA = 0° C to 70°C, Vcc = 5.0V±5% Military TA = -55°C to 1 25° C, Vcc = 5.0V±1 0%
Cload = 50 pF, Rload = 500Q unless otherwise noted
Symbol
Description
Note
Com
Mil
Unit
Min
Max
Min
Max
t PLH
t PHL
Data Propagation Delay
Ai to Bi, Bi to Ai
338X
2,3
0.25
0.25
ns
358X
2,3,7
1.25
1.25
ns
tPZH
t PZL
Switch Turn On Delay
BEA, BEB to Ai, Bi
338X
1
1.5
6.5
1.5
7.5
ns
358X
1,7
1.5
7.5
1.5
8.5
ns
t PLZ
t PZL
Switch Turn Off Delay
BEa, BEB to Ai, Bi
338X
1,2
1.5
5.5
1.5
6.5
ns
358X
1,2,7
|Qd|
Charge Injection, Typical
338X
4,6
1.5
1.5
pC
358X
4,6,7
Notes:
1) See Test Circuit and Waveforms. Minimums guaranteed but not tested.
2) This parameter is guaranteed by design but not tested.
3) The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and
the toad capacitance. The time constant for the switch and aloa alone is of the order of 0.25 ns for 50 pf load.
Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little
propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by
the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
4) Measured at switch turn off, A to C, load - 50 pF in parallel with 10 meg scope probe, Vin at A - 0.0 volts.
5) Characterized parameter but not 100% tested.
6) Characterized parameter. Not 1 00% tested.
7) Preliminary data, subject to change.
QUALITY SEMICONDUCTOR INC.
5-27
i
I
r
QUALITY
INC.
General Information 1
Static RAM Products 2
FIFO Memory Products 3
FCT Logic Products 4
QuickSwitch Products 5
Quality And Reliability 7
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
QUALITY SEMICONDUCTOR INC.
Application Notes
APPLICATION NOTES
Page
AN-01 Ground Bounce Noise in TTL Logic 6-3
AN-02 FIFOs as High Speed Data Queues for Systems 6-21
AN-03 The 6-Transistor SRAM Cell and Its Advantages 6-35
AN-04 High Speed SRAMs and Bus Contention Issues 6-41
AN-05 High Speed SRAMs in Cache and Bit Slice Applications 6-47
AN-06 ZIP Packages for Logic Provide High density and High Speed 6-59
AN-07 Resistor Output Logic Gives High Speed with Low Noise 6-61
AN-08 QSOP Packages Provide High Density in 32-bit Bus Designs 6-63
AN-09 CMOS Bus Switches Provide Zero Delay Bus Communication 6-65
QUALITY SEMICONDUCTOR INC.
Application Notes
■
6-2
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise In TTL Logic
=
Q
Ground Bounce Noise
in TTL Logic
Application
Note
AN-01
By David C. Wyland
High speed TTL octal drivers such as the FCT244 can generate ground bounce noise when driving
capacitive loads at high speed. On the FCT244, ground bounce occurs when seven of the eight outputs
are switching high-to-low with a high capacitance load, and the eighth output is held a constant low. In this
case, the high-to-low transition of the outputs causes capacitive current (l=CdV/dt) to flow in the single
ground lead of the FCT244. This current pulse causes a voltage pulse to appear (V=Ldi/dt) across the
package inductance of the ground lead. This voltage pulse on the unchanging low output is called
ground bounce noise. This voltage pulse will appear on the output that is held low, since it shares the
common ground pin.
Ground bounce noise is a concern of the system designer because it can affect other circuits in a design.
Ground bounce is a chip design problem with system implications. The chip designer tries to achieve the
highest speed with an acceptable level of ground bounce. The system designer needs to understand
the limits of the combination of chip and package technology represented by ground bounce to know
what to expect from future designs. A ground bounce model is a useful tool for achieving these goals. In
this paper, we will study ground bounce using an RLC resonant circuit model.
Ground Bounce Example
Figure 1 shows a test setup which allows ground bounce to be measured, and Figure 2 shows typical
results.
Pulse
DO
YO
D1
Y1
D2
Iver
Y2
D3
D4
FCT244
Octal Dr
Y3
Y4
D5
TTL
Y5
D6
Y6
D7
Y7
jlH>
50 pf
Oscilloscope
Figure 1: Ground Bounce Test Setup
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise In TTL Logic
1 V
/dlv
5V
■ntf
J ■,
».* I I II I II
tttt]
H i rrl
[ 1 1 1 1 l
w
hmr
TTTT
TTTT
hrrH
1 1 1 1 1
1
1
>
5 ns/div
Figure 2: Ground Bounce Noise Oscilloscope Trace
Problems Caused by Ground Bounce In TTL System Designs
Ground bounce noise is a problem when it couples into other circuits or when it upsets the operation of
the IC that generates it. Ground bounce noise is a problem in bus driver chips when the unswitched
output is a control signal used to enable or clock other circuits. Ground bounce is not a problem in data or
address bus driver circuits where all outputs switch and settle at the same time and their associated
circuitry waits until the signals are settled before sampling them. Ground bounce is an indirect problem in
these cases to the extent that it increases system noise and corresponding settling times in general.
Ground bounce noise is a problem only if it affects the circuits it drives. Whether driven circuits are
affected is determined by the difference between the ground bounce pulse size and duration and the
dynamic (AC) noise margin of the driven circuit. Dynamic noise margin is a function of the logic family of
the driven circuit: i.e., LS, AS, F, HCT, etc. A plot of dynamic noise margin for various TTL logic families
and showing typical ground bounce pulses is shown in Figure 3.
Ground bounce is associated with high-to-low switching in TTL designs. In the high-to-low (ground
bounce) case, the unswitched output is connected directly to ground. The ground bounce spike from
the internal ground is coupled directly to the output. In the low-to-high (Vcc bounce) case, the
unswitched output is either connected directly to the internal Vcc in a CMOS output or buffered from Vcc
by a source- or emitter-follower transistor in the TTL output case. In the CMOS output case, the Vcc
bounce noise margin is (5-1 .5) = 3.5 volts, more than twice the ground bounce margin. In the TTL output
case, the source/emitter-follower buffer isolates the VCC bounce from the actual output.
6-4
QUALITY SEMICONDUCTOR INC.
=
AN-01: Ground Bounce Noise In TTL Logic
bbbbb=ss:sssss:bbsbbb=bss=^=
Pulse Width, ns
Figure 3: Dynamic Noise Margin of Various TTL Logic Families
Problems Caused by Ground Bounce In TTL Chip Designs
Ground bounce has significance for the chip as well as the system. When a ground bounce pulse is
generated, the chip ground voltage is changed relative to the outside, system ground. Since the inputs
to the chip are referenced to system ground, they appear to change relative to the chip ground as a result.
During the positive portion of the ground bounce pulse, the internal ground is raised. This makes the
inputs appear as though they have a negative pulse added to them equal to the ground bounce pulse. If
the ground bounce pulse is large enough and the driving circuit has a low Voh, the high inputs would be
pulsed below their thresholds. This can cause false clocking on register parts such as FCT374, etc. and
false clocks and reset pulses on FIFOs such as 512x9 devices. It can also cause noise pulse injection on
RAM address lines. This can result in longer access times because of disturbance of the address
decoders and reactivation of the address transition detect circuitry.
After the positive portion of the ground bounce pulse, there is a negative, undershoot portion
approximately equal in size to the ground bounce pulse. This makes the internal ground fall and causes
logic low inputs to appear as though they have a positive pulse on them. This can cause false clocking on
latch devices such as FCT373 which require their latch inputs to remain low to retain data. This
undershoot pulse can also cause double clocking on registers and FIFOs during the time the clock pulse
QUALITY SEMICONDUCTOR INC.
6-5
AN-01: Ground Bounce Noise in TTL Logic
is held low. The undershoot pulse causes an effective positive spike on the clock line, resulting in a
second clock pulse. Undershoot can also cause noise pulse injection on RAM address lines.
Specifying Ground Bounce In TTL System Designs
Ground bounce is the result of an interaction of high speed TTL circuits with their packages. It has
become significant because of increased TTL speed. Because ground bounce is a result of speed, there
is an inherent tradeoff between speed and ground bounce. Ground bounce can be optimized but not
eliminated. For this reason, high speed TTL logic should have a ground bounce specification.
A ground bounce specification should balance the need for speed against the need for noise margin.
Defining an acceptable level of ground bounce must take both speed and the driven logic family into
consideration. Speed and ground bounce are related. Lower ground bounce means lower speed for a
given logic family, so ground bounce should not be arbitrarily set at some low value. However, once a
ground bounce noise problem enters a design, it can be at least as difficult as other system noise
problems to diagnose and solve.
Ground bounce can be "designed around" if necessary. In a typical system design, perhaps 2% of the
design will be sensitive to ground bounce. For example, address and data bus drivers and receivers will
not be directly sensitive to ground bounce, except for the additional system noise that ground bounce
generates. A good system designer can avoid and/or compensate for potential ground bounce
problems. This, however, is not desirable. Good system designers are too scarce and valuable to spend
their time compensating for chip vendors' problems unless there is no other choice. Also, designers
implementing engineering changes may not have access to the original designer's thinking on how to
avoid ground bounce problems in the design.
Referring to Figure 3, a ground bounce peak value of 1.5 volts for nominal pulse widths in the 3-5 ns
region is a reasonable ground bounce specification for many designers. This pulse will be below the
threshold of CMOS TTL logic families and just at the threshold for bipolar TTL such as 74F devices. If the
ground bounce pulse is 1 .5 volts or below, it should not propagate through bipolar TTL devices.
-
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise in TTL Logic
Ground Bounce RLC Simulation Model
Ground bounce can be modeled for SPICE analysis as shown in Figure 4. This diagram represents an
octal device such as an FCT244, with 7 of 8 outputs switching high-to-low and the 8th output unswitched.
Seven of the eight load capacitors have been charged to Voh and are discharged through the ground
lead inductance when their respective transistors switch. The eighth transistor remains on as the
unswitched output.
H
Switched Outputs (7)
Loutput Ron
Loutput Ron
-mm — 'w
4-10 nH
Q2-8 Each
5a Each
H
Unswitched Output
Cload
50 pF -r~
Each
Loutput
-fYYYV
Q1
h
Lgnd
13 nH
Ron
^N/S/
4-10 nH 5Q
Cload
50 pF _
Figure 4; Ground Bounce Circuit
■
Rload
500£2
Each
Rload
500S2
■
QUALITY SEMICONDUCTOR INC. 6-7
AN-01: Ground Bounce Noise In TTL Logic
A simplified RLC model of the circuitry of Figure 4 is shown in Figure 5. In this figure, all eight outputs are
assumed to be switching for maximum ground bounce. Since the load capacitors, load resistors, and lead
inductances are effectively in parallel, their nominal values per pin are divided by eight. The ground
inductance is in common with ail, its value remains unchanged. Ground bounce appears across the
ground lead inductance, Lgnd. The series inductances per pin have been eliminated. This is done to
simplify the model. It can be done because their paralleled value is small with respect to Lgnd, and
ignoring them will result in ground bounce values at least as bad (generally 2-5% worse) as if they were
included.
Output Switching Transistor as a Voltage Ramp Generator
In the RLC model above, the high-to-low switching action of the output transistors has been replaced by a
voltage ramp generator, Vin. This is one of several simplified models, such as modeling the switch as a
current ramp generator or a simple switch with a variable series resistance. Voltage ramp generators are
easy to model in SPICE, and node voltages are the usual variables that are observed and controlled by the
designer. The most important consideration, however, is that when high current capability CMOS outputs
are modeled as voltage ramp generators in the RLC model, the results correspond very well with observed
data.
High speed CMOS based TTL devices act like voltage ramp generators. Their output fall time does not
vary appreciably over the range of 5-50 pF. If they were current sources or current limited voltage sources,
one would expect the fall time to be proportional to the capacitance, at least above some value.
Examining the current required to drive ground bounce in these high drive (typically above 100 mA)
CMOS devices is instructive.
To verify whether the outputs are current limited during the ground bounce, consider the current built up
in the ground inductance at the peak of the ground bounce pulse. This current is the integral of the
ground bounce pulse divided by the inductance. If we consider the ground bounce pulse to be a half-
sine wave, the inductor current at its peak is:
lypeak = (GB Peak voltage)(1/2 GB Pulse Width) (Average Value of a half-sine wave) / (Lgnd)
= 0.31 9(GB peak voltage)(GB Pulse Width) / (Lgnd)
= 0.319(1.5)(5.0)/(13) = 0.184 IB = 23 mA per output for a 1 .5V. 5 ns nulse
We are not particularly interested in the current after the voltage peak because it can cause no further
increase in ground bounce. Knowing the peak current, we can calculate the maximum ground bounce
Ron = 5/8 O
^V\/ T 1
Figure 5: RLC Ground Bounce Model
6-8
QUALITY
INC.
AN-01: Ground Bounce Noise In TTL Logic
pulse width where the outputs can still be considered to be voltage ramp controlled. If the saturation
current is given by l0l, this will be given by:
l0l - lypeak = 0.31 9(GB peak voltage)(GB Pulse Width) / (Lgn(j)
GB Pulse Width = l0l / 0.319(GB peak voltage) = 3.14 (l0l XL^) / GB peak voltage
For high speed CMOS parts such as the FCT series, the outputs are rated at 64 mA, and are typically
capable of more than twice this rating in order to guarantee DC specifications over the temperature range.
Using a value of 128 mA per output as the current limit and 13 nanohenries as the ground lead inductance
gives the following values for the maximum ground bounce pulse width before current limit.
GB Pulse Width = 3.1 4 (8 x 0.1 28) (13)/ (GB peak voltage)
= 41 .82 / (GB peak voltage)
= 41 .8 ns @ 1 .0 volt peak ground bounce
= 27.8 ns @ 1 .5 volts peak ground bounce
= 13.9 ns @ 3.0 volts peak ground bounce
These values are significantly above typical ground bounce pulse widths, which are in the 3-5 ns range.
This tends to support the voltage ramp model for the high speed, high current devices used in TTL
devices with significant ground bounce.
PLC Model vs Actual Waveforms
The validity of the RLC model can be determined by comparing a plot of the model output for appropriate
values of R, L, C, and fall time versus results measured in the laboratory. Figure 6 shows a plot of the RLC
model output using nominal values for nominal CMOS circuit resistance and fall time for an FCT244 in a
300 mil plastic DIP package. The ground bounce results shown are for all eight outputs switching; for 7 of
8 switching, the ground bounce values are multiplied by 7/8.
Figure 7 shows a plot of laboratory data recorded for a commercially available FCT244 device using the
configuration of Figure 1 . A high performance ground bounce test jig was used and the results recorded
and plotted using a 1 gHz bandwidth sampling oscilloscope. The RLC model data in Figure 6 compares
reasonably well with the recorded data in Figure 7.
>
I
QUALITY SEMICONDUCTOR INC. 6-9
AN-01: Ground Bounce Noise In TTL Logic
■
-1
■2
-3
-4
-5
. *■
■
La
► • ♦ ♦■
• ♦ ♦ ♦
■ ♦ ♦ ♦ ♦
Vgnd
1
■
2 4 6 8 10 1214 16 1820
Time - ns
Values Used: Inductance 13 nanohenries
Capacitance 50 pF/output
Resistance 5 n/output
Voh 3.50 Volts
Fall Time 5 ns, 3.5 V to 0 V
Figure 6; RLC Model Ground Bounce Waveforms
■
■
— Volp
■o-Vhl
Figure 7; Measured Ground Bounce Data for QSFCT244
=
6-10
QUALITY SEMICONDUCTOR INC.
assess
AN-01: Ground Bounce Noise in TTL Logic
=============================
RLC Model Simulation Study
Using the RLC model, a simulation study was performed using various values of R, L, C, and output fall
time (Tf) to reveal their effect on ground bounce and propagation delay. Given the RLC model, several
useful observations can be made before simulations are begun. These are as follows.
Ground Bounce is Proportional to Voh.
Ground bounce is the result of discharging the load capacitance through the package inductance. Since
the load capacitance is charged to Voh, the ground bounce will be directly proportional to Voh.
Tphl Reduces with Voh
Reducing Voh reduces the voltage swing required to reach threshold as a percentage of the total logic
swing. For a given total fall time, the time to go from Voh to threshold is reduced as Voh is reduced. An
extreme example would be if Voh were 1 millivolt above threshold, yielding a Tphl of nearly zero.
Ground Bounce Proportional to the Number of Outputs Switching
Ground bounce is the result of discharging the load capacitance through the package inductance. If all
outputs switch, ground bounce reaches its full value. If some of the outputs switch and some are held
low, there will be charge sharing between the capacitors at the beginning of the switching interval with the
capacitors charged to Voh sharing charge with those that are not. After charge sharing, the effective Voh
is equal to the actual Voh times the ratio of the number of outputs switching to the total number of
outputs. I.e., if only half the outputs switch, the effective Voh will be half the nominal Voh.
Ground Bounce is a Non-linear Function of Tf, R, L, C
The RLC circuit forms a two pole high pass RLC filter for ground bounce. The typical fall time of the CMOS
circuits of interest (3-5 ns) is similar to the RLC resonant time constant (70 mHz => 2.28 ns). Ground
bounce will therefore be a function of the fall time relative to the resonant frequency as determined by R,
L, and C. Changes in the resonant frequency are generally proportional to the square root (i.e.,
zsszis^^s^s^^ an addifonal term under the square root sign- Simple
Tphl has a lower limit determined by the resonant frequency of the RLC circuit
The output of the TTL device appears across the load capacitor, not across the switch. Since the load
capacitor is part of a resonant circuit, its rise and fall time will be limited by the resonant frequency of the
RLC circuit. The minimum fall time as seen by the load will be the time required for the capacitor to reach
(Voh-Vthreshold). If the threshold is half the logic swing (Voh = 3.0 V), this will correspond to COS"1 (0.5)
= 60°. The minimum propagation delay will therefore be (60/360)*(1/70 mHz) = 2.38 ns.
=
QUALITY SEMICONDUCTOR INC. 6-11
AN-01: Ground Bounce Noise in TTL Logic
=
=
RLC Model Simulation Results
Ground Bounce vs Fall Time and Resonant Frequency
Figure 8 shows a plot of ground bounce voltage, Volp, as a percentage of Voh versus fall time as a fraction
of the resonant time constant, i.e. Tf vs 1/2jrvCC. This is a plot for various values of package inductance
(L), load capacitance (C) and fall time (Tf) with R=5i2 for the on resistance of the CMOS switch. Using the
resonant frequency of the load capacitance and the package inductance allows the graph to be
normalized for these various values.
100%
Volp/Voh
10% I 1 1 1 I I I I I I 1 1 1 — I I I II I
0.10 1.00 10.00
Fall Time vs Resonant Time Constant = Tf/VLC
Figure 8: Ground Bounce vs Fall Time Relative to Resonant Time Constant
The plot of the data shows a high pass filter function with the ground bounce decreasing as the fall time
increases. When the fall time is small relative to the resonant time constant, the ground bounce
approaches Voh as an asymptote.
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■
6-12
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise In TTL Logic
^^=== ============== =====
Ground Bounce vs Package Inductance
Figure 8 is instructive as an overview, but it is more instructive to examine how we can affect ground
bounce by varying specific parameters such as package inductance, etc. Figure 9 shows a plot of ground
bounce versus package inductance for a fixed fall time of 5 ns and a fixed load capacitance of 50 pF per
output.
100% ■
90% ■
8 0 /o
70% ■
60% -
Volp/Voh 50% ■
40% -
30% -
2 0% ■
10% -
0%-
0 5 10 15 20 25 30 35
L • Package Inductance, Nanohenries
Figure 9: ground Bounce vs Papkaqe Inductance
As the chart shows, ground bounce goes up with inductance. Increasing inductance decreases the
resonant frequency. This increases the resonant time constant, decreases the ratio of fall time to this time
constant , and therefore increases the ground bounce. Since resonant frequency is a function of the
square root of the inductance and capacitance, cutting the inductance in half does not cut the ground
bounce in half, as some simpler models show.
*€o\c, ; ip
QUALITY SEMICONDUCTOR INC.
6-13
AN-01: Ground Bounce Noise In TTL Logic
Ground Bounce vs Load Capacitance
Figure 1 0 shows a plot of ground bounce versus load capacitance for a fixed package inductance of 1 3
nanohenries, a fixed fall time of 5 ns, and a series resistance of 5Q.
0 50 100 150 200 250 300
C - Load Capacitance per Output, Pf
Figure 10: Ground Bounce vs Load Capacitance
As the chart shows, ground bounce goes up with capacitance. Increasing capacitance decreases the
resonant frequency. This increases the resonant time constant, decreases the ratio of fall time to this time
constant , and therefore increases the ground bounce. Since resonant frequency is a function of the
square root of the inductance and capacitance, cutting the capacitance in half does not cut the ground
bounce in half, as some simpler models show.
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise In TTL Logic
Ground Bounce ys Series Resistance
Adding series resistance will reduce ground bounce. The added series resistance increases the total
impedance in the RLC current loop, reducing the current in both L and C. This causes the decrease in
ground bounce. It also causes an increase in propagation delay because increasing the resistance
increases the damping factor of the resonant circuit, lowering its resonant frequency. If the added
resistance is less than the critical damping resistance a significant decrease in ground bounce can be
traded for a small increase in propagation delay.
The following figures show the results of adding series resistance. Figure 1 1 shows a plot of ground
bounce versus load capacitance for L = 13 nanohenries, Tf = 5 ns, and series resistances (R) of 5Q and
25Q. Figure 12 shows a plot of relative ground bounce reduction versus series resistance.
80%
70%
60%
50%
Volp/Voh 40%
30%
20%
10%
0%
I —
— o
r
rf i
— C + 25Q.
50 100 150 200 250 300
Load Capacitance per Output, Pf
Figure 11: Ground I
GB/GB@4£2
■-25 pF
O- 50 pF
-100 pF
•©■200 pF
-a- 300 pF
0 1 0 20 30 40 50 60 70 80
R = Series Resistance, a
Figure 12: Ground Bounce vs Series Resistance
QUALITY SEMICONDUCTOR INC.
6-15
AN-01: Ground Bounce Noise in TTL Logic
Figure 13 shows a plot of propagation delay versus series resistance for various values of capacitance and
for L = 1 3 nanohenries and Tf = 5 ns. This is a minimum propagation delay and is the delay associated
with the resonant RLC circuit, as derived from the simulations.
Tphl/Tphlz
-25 PF
■D-50 pF
-♦■100 pF
■0-200 pF
-'-300 pF
25 50 75
Series Resistance, Q
100
Figure 13: Propagation Delay vs Series Resistance
As can be seen from the figure, the propagation delay rises slowly with damping resistance below 50
ohms, above which it rises rapidly for high capacitance loads. This is because the resistance has risen
above the critical damping resistance for the resonant circuit for these loads. Above the critical damping
resistance, the circuit is no longer resonant, ground bounce becomes proportional to the L/R time
constant and propagation delay becomes proportional to the RC time constant. To determine this point,
Figure 1 4 shows a plot of critical damping resistance versus load capacitance.
1000
Rent, a 100
•■-5 nH
■D-13 nH
0 50 100 150 200 250 300
Capicitance/Pin, pF
Figure 14; Critical Damping Resistance vs Load Capacitance
6-16
QUALITY SEMICONDUCTOR INC.
AN-01: Ground Bounce Noise In TTL Logic
Propagation Delay vs Ground Bounce
Given the above data, we can plot propagation delay versus ground bounce. Figure 15 shows such a plot
for the case of Voh = 3.5 volts, L = 13 nanohenries and C = 50 pF/pin. In this figure, the main curve plots a
relationship between ground bounce and propagation delay for various combinations of fall time (Tf) and
series resistance (R).
Note that below the critical damping resistance of 91 £2 for 50 pF & 13 nH, either series resistance or fall
time can be used to trade ground bounce for propagation delay.
100% T
90%
80%
70%
60%
Volp/Voh 50%
40%
30%
20%
10%
0%
1
■
ri
■-50 pF, 5£2
■O-50 pF, 16Q
— 50 pF, 25Q
-©-50 pF, 50Q
-'-50 pF, 100O
3 4 5 6 7 8 91011
Propagation Delay, Tphl, Nanoseconds
Voh = 3.50 volts
Figure 15; Propagation Delay vs Ground Bounce
s
QUALITY SEMICONDUCTOR INC.
6-17
AN-01: Ground Bounce Noise in TTL Logic
We can use the above data to show the tradeoff of ground bounce versus propagation delay as a function
of the series resistance. The curves of Figure 1 6 plot the slope of the ground bounce versus propagation
delay curve; i.e. the percent decrease in ground bounce divided by the percent increase in propagation
delay as a function of series resistance relative to the critical damping resistance.
Ground Bounce vs Tphl Tradeoff vs R
3.5
3.0
2.5
AGB/ATphl 2.0
1 .5
1 .0
0.5
0.0
*
V-
*****
— ♦
0.0 0.2 0.4 0.6 0.8
R/Rcrltlcal
1 .0
1.2
■-25 pF
■O-50 pF
— 100 pF
-O-200 pF
-*-300 pF
Figure 16; Ground Bounce vs Propagation Delay Tradeoff versus Resistance
For small values of series resistance, ground bounce decreases faster than propagation delay increases.
For values in the 5-1 0Q range at 50 pF loading, a 1 % increase in propagation delay can be traded for a
3.5% decrease in ground bounce. One-half the critical damping resistance is the break-even point. For
resistance values above this value, propagation delay increases relatively faster than ground bounce
decreases. This implies that the series resistance should be less than half the critical damping resistance
for the largest expected capacitive load.
6-18
QUALITY SEMICONDUCTOR INC.
1
AN-01: Ground Bounce Noise In TTL Logic
Propagation Delay and Ground Bounce vs Voh
Propagation delay increases with Voh because the output must travel a larger voltage difference between
Voh and the TTL threshold. Ground bounce is directly proportional to Voh. This is shown in the plot of
ground bounce versus high-to-low propagation delay for three values of Voh shown in Figure 1 7. The
plot in Figure 16 is for L = 13 nanohenries, C = 50 pF/pin, and various values of Tf.
Note that the high-to-low propagation represents the minimum delay associated with the RLC resonant
circuit. Propagation delay for other circuitry must be added to this for actual delays.
Propagation delay for other values of L and C for a given ground bounce can be calculated using this chart
and multiplying the Tphl value by the square root of the ratio of L or C to 13 nH and 50 pF, respectively.
Volp vs Tphl for 13 nH (PDIP) and 50 pF/pin Load
Volp, Volts
4.50
4.00
3.50
3.00
2.50
2.00
1 .50
1 .00
0.50
0.00
**
H
*
^3
I
"A — -
-A
23456789
Propagation Delay, Tphl, Nanoseconds
Figure 17= Ground Bounce vs Propagation Delay and Voh
---2.5V, 5Q
-D-2.5V, 25Q
— 3.5V, 5Q
"©■3.5V, 25Q
-»-4.5V, 5Q
•A- 4.5V, 25CI
QUALITY SEMICONDUCTOR INC.
6-19
AN-01: Ground Bounce Noise in TTL Logic
Propagation Delay and Ground Bounce for Shaped Drive Pulses
Propagation delay for a given ground bounce can be improved if a shaped drive pulse other than a linear
ramp is used. Propagation delay is determined by the rate of voltage build up on the load capacitor, which
is determined by the rate of current build up in the ground inductor. To improve the propagation delay,
you increase the ramp rate of current in the inductor.
The maximum possible current ramp rate in the inductor is determined by the inductance and the ground
bounce by the rule V = L dl/dt. This could be achieved by using a current ramp instead of a voltage ramp
and adjusting the ramp rate for the allowed ground bounce. The current ramp is adjusted so that the
ground bounce pulse rises immediately to the desired ground bounce value and stays there until the
output has achieved the high-to-low transition.
The propagation delay time for a current ramp equal to Volp/L is determined by the capacitance and the
difference between Voh and the 1.5 volt TTL threshold by the relationship:
V = (Voh-1.5) = Q/C
Q = JJ dl/dt = JJ (Volp/L)dt = (1/2)(Volp/L)Tphl2
Tphl = SQRT(2*L*C*(Voh-1.5)/Volp).
This represents the best possible propagation delay for a given RLC circuit and required ground bounce.
A plot of ground bounce versus propagation delay for these conditions is shown in Figure 18. Ground
bounce values were limited to 1 .5 volts, the threshold voltage, for ease of analysis.
■
As in Figure 17, propagation delay for other values of L and C for a given ground bounce can be
calculated using this chart and multiplying the Tphl value by the square root of the ratio of L or C to 1 3 nH
and 50 pF, respectively, as indicated by the above equation.
Volp vs Tphl for 13 nH (PDIP), 50 pF/pIn Load, dl/dt Drive
1.60
1 .40
1 .20
1 .00
Volp, Volts 0.80
0.60
0.40
0.20
0.00
■
N \
A
—
^si
■-2.5
Voh
■D-3.0
Voh
— 3.5
Voh
■0-4.5
Voh
2 3 4 5 6 7 8
Propagation Delay, Tphl, Nanoseconds
Figure 18: Ground Bounce vs Tohl and Voh for Ground Bounce Determined dl/dt
6-20
QUALITY SEMICONDUCTOR INC.
AN-02: FIFOs as High-Speed Data Queues for Systems
Q
FIFOs as High-Speed Appl,c5'°t!!
Data Queues for Systems AN.02
by
Suneel Rajpal
Introduction
A FIFO is a queue for data. FIFO means First-In-First-Out, the definition of a queue. FIFOs are used to
queue data between parts of a system that generate and receive data at different rates and times. For
example, to read data from a disk, you must be able to accept the data as it passes under the read head.
This means accepting data on demand, usually at a high rate, for transfer to main memory at a more
moderate rate when the main memory is ready to accept it. Unique design features and a variety of
applications of FIFO integrated circuits will be discussed in this application note.
What is a FIFO ?
A short definition of a FIFO is as a queue for data. Queues are observed in everyday life in toll stations and
airline check-in counters. In computer applications a data queue is required when data must be
transferred between parts of a system which operate at different data rates. Often data is generated (or
required) in bursts faster than it can be absorbed (or generated). The FIFO provides a temporary holding
area for data to service these data bursts.
FIFOs are specially designed integrated circuits. They are designed as the hardware equivalent of the
circular buffer concept used in software. They consist of a special, dual-port memory that can be read and
written at the same time, and address counters for reading and writing. The counters treat the memory as
though it were circular: location zero immediately follows after the last location in memory. When a counter
has reached the last word in the memory, the next increment takes it to the first word.
In the circular buffer concept, data is written at the address selected by the write counter, and the counter
is incremented after the write. After data is written, data is read separately from the address selected by
the read counter, which is incremented after the read. The read counter thus follows the write counter
continuously around the memory. If the read counter catches up to the write counter, the FIFO is said to
be empty. If the write counter catches up to the read counter, the FIFO is said to be full. These full and
empty conditions are detected by the flag logic, which compares the contents of the two counters.
A block diagram of the QSI FIFO family is shown in Figure 1. The FIFO devices have separate read and
write pointers that are clocked by the respective read and write signals. Flag indicators such as full, empty,
and half full are also provided.
FIFOs have widths and depths similar to RAM memories. Width is the number of bits per word. Depth is
the size of the circular memory in words, usually a binary multiple such as 512 words, etc. QS FIFOs are
available in 512x9, 1Kx9, 2Kx9, 4Kx9. The part numbers are QS8201, QS8202, QS8203, QS8204
respectively. Two or more FIFOs can be combined to increase the effective width of the FIFO. This is
simple; the FIFOs are operated in parallel, and no interaction is needed between the FIFOs.
===========
QUALITY SEMICONDUCTOR INC.
6-21
AN-02: FIFOs as High-Speed Data Queues for Systems
W
WRITE
CONTROL
READ
CONTROL
R3
FL7RT
XI
RESET
LOGIC
EXPANSION
LOGIC
WRITE
POINTER
READ
POINTER
FLAG
LOGIC
EF
FF
HF
XO"
DATA IN
DCM38
DUAL PORT
RAM ARRAY
512X9
1024X9
DATA OUT
Q0-Q8
Figure 1 . FIFO Block Diagram
Two or more FIFOs can be combined to increase the effective depth of a FIFO. This is called depth
expansion. This requires using additional logic to pass data between the FIFOs. QSI FIFOs contain logic
to provide depth expansion without additional logic or speed penalties. Depth expansion of QSI FIFOs is
done by using the expansion in and expansion out signals.
FIFOs must be initialized before use because the read and write counters can come up with random
values at power-up. This is done by a reset operation. A pulse on the reset (RS) pin clears both counters
to feature zero, making the FIFO empty. QSI FIFOs also provide a partial reset called retransmit. A pulse
on the retransmit input resets the read pointer to zero. Retransmit allows data written into the FIFO to be
re-read. One application is in communications, where data may need to be retransmitted because of an
error in the first transmission.
FIFOs designed using a dual port RAM with read and write address counters are said to be pointer based,
to differentiate them from earlier FIFOs based on different principles. Pointer-based FIFOs have the
advantage of zero fall through time, the time required to receive an output from an initially empty FIFO
after the first write operation.
Figure 2 shows a diagram of the FIFO as a circular queue with two pointers. After power up both read and
write pointers are reset to zero. After that, upon write operations, the write pointer is incremented. The
numbers outside the circle indicate the values the pointers can have. For example the write pointer
increments from 0 to 1023 and then wraps to 1024 on the next write. The shaded area indicates the
number of words in the FIFO. When a read operation is performed, the read pointer is incremented. When
the read pointer equals the write pointer after the completion of a read operation, the FIFO is empty. If the
write pointer equals the read pointer after the completion of a write operation, then the FIFO is full. When
the FIFO contains more words than half its depth, the half full flag is asserted.
AN-02: FIFOs as High-Speed Data Queues for Systems
0/1024
768
Figure 2. A 1 Kx9 FIFO as a Circular Buffer
Width Expansion
FIFOs can expand in width without any external logic. A 1Kx18 FIFO array is shown in Figure 3. Data is
entered into all of the FIFOs using one write signal. Data is read from all of the FIFOs using one read
signal. The expansion in input XT is grounded. The flags can be monitored from any FIFO, as both FIFOs
will track each other.
1
QUALITY SEMICONDUCTOR INC.
AN-02: FIFOs as High-Speed Data Queues for Systems
Data In 0-8
Write Clock
Reset
Data Out 0-8
Read Clock
Retransmit
Data In 9-17
Full Flag <4-
-► Empty Flag
Half Full Flag
Figure 3: Width Expansion - An 18-bit FIFO From Two 9-bit FIFOs
Depth Expansion
FIFOs can be expanded in depth fairly easily. As FIFOs do not have chip selects, another mechanism
must be used to identify the first FIFO that will be written to or read from. The FC or first load signal
indicates which FIFO will receive the first N words or transmit the first N words after a reset operation where
N is the depth of a single FIFO. Figure 4 shows FIFOs in a depth expansion mode. One FIFO in the array
has its FC line grounded and the other FIFOs have their FC line at Vcc. The expansion output of one FIFO
is connected to the expansion in of the other FIFO and so on until the expansion out of the last FIFO is
connected to the expansion of the first FIFO. It is good system practice to layout the FIFOs so that the
trace length of the expansion out of the last FIFO is connected to the expansion in of the first FIFO. It
should be kept small to minimize crosstalk effects.
6-24
QUALITY SEMICONDUCTOR INC.
AN-02: FIFOs as High-Speed Data Queues for Systems
=
DEPTH EXPANSION
(COMPOSITE)
FF
DATA IN 0-8
9 DATA OUT
0-8
9
Figure 4. Building a 4-N deep FIFO out of an N-deep FIFO
The FIFO operates elegantly in depth expansion . After a reset operation the FIFO with the Frgrounded
receives the first N words. On the writing on the Nth word a pulse is sent on the XO" output to the input of
the next FIFO. The N+1th word is written into the next FIFO. Similarly the first N reads take place in the
first FIFO. On the Nth read a pulse is sent from the XO~output to the input of the next FIFO. This allows
the N+1th word to be read from the next FIFO. Similarly when the 2N words are written the 2N+1th write
takes place in the third FIFO. Finally when the control is transferred to the last FIFO in the queue and it too
reaches its boundary, the write control is passed back to the first FIFO. This is shown for a configuration
with two FIFOs in Figure 5. Some external logic, (namely OR gates) is required to combine the individual
empty flags to give a composite empty flag, and the individual full flags to give a composite full flag.
QUALITY SEMICONDUCTOR INC.
6-25
AN-02: FIFOs as High-Speed Data Queues for Systems
5
After reset
After some writes
After 512 writes
and some reads
XO After further reads
and writes
After 512 reads
After 1024 writes
1 1 ■— XO
After further reads
and writes
After 1024 reads
After 1536 writes
Figure 5. The Expansion Signals for a 1 Kx9 FIFO using two 51 2x9
i!
AN-02: FIFOs as High-Speed Data Queues tor Systems
Operating on Boundary Conditions
The conditions where the FIFO is empty or full is called a boundary condition. When the FIFO becomes
empty and read signals are still applied, the FIFO ignores the signals. The output remains in high
impedance when the FIFO is empty. A write operation ends the empty condition and a read pulse equal to
the read pulse width minimum must subsequently be applied after the empty flag goes high. This is
demonstrated in Figure 6. This is required due to an internal mechanism that forces the internal read
signal high on the empty condition. A similar write pulse width minimum specification must be met for
operations ending the full condition. When the FIFO is full and the write signal is toggling, if an
asynchronous read operation occurs, a write pulse greater than the write pulse width minimum must be
applied to achieve proper operation. The FIFO similarly ignores write signals when it is full. This is shown
in Figure 7.
rea^ \ r~}\ / v
Note 1
WRITE
~\ f
EMPTY FLAG
V
t1, Note 2
r
—
-
Note 1. This read pulse is ignored as the FIFO is empty at
this time.
Note 2. The pulse width t1 must be more then tRPW, the minimum
read pulse width to ensure proper operation.
Figure 6. Boundary Condition on an Empty FIFO.
■
■
■
■
-
QUALITY SEMICONDUCTOR INC.
6-27
AN-02: FIFOs as High-Speed Data Queues for Systems
WRITE
Note 1
READ
FULL FLAG
\
J
t1, Note 2
Note 1. This write pulse is ignored as the FIFO is full at
this time.
Note 2. The pulse width t1 must be more then tWPW, the minimum
write pulse width to ensure proper operation.
Figure 7: Boundary Conditions on a Full FIFO.
Why does one need to meet these timing specifications? The read and write signals are clock signals to
the pointers. If the minimum pulse widths are not met, this can cause the counters to run erroneously and
erratically, a condition recoverable only by a reset operation.
FIFO Applications
DMA Operations
FIFOs can be used as part of DMA controllers. In DMA operations, data is accessed from a slower
peripheral bus and transferred to a memory location. In certain applications, a DMA controller may have to
acquire two buses, one on which the memory resides and the second on which the peripheral resides and
then perform the transfer. If a slower peripheral is on one of the buses it can reduce the performance of
the second bus where the faster memory resides due to a higher bus utilization rate during DMA transfers.
One way to improve the performance is to have the FIFO interface to the peripheral device and transfer
data from the peripheral at the peripheral's frequency in a burst manner. The output of the FIFO can
interface to the system bus at higher speeds via transceivers. Since the FIFO can be clocked at a higher
frequency than its input frequency, the external bus utilization rate can be reduced. For example, if a
block of 1 K words has to be transferred, the peripheral can transfer the data to the FIFO. The FIFO can
signal to the DMA controller that it has 51 2 or 1 K words of data via the half-full or full flag. Then the FIFO is
read in a burst manner. In this mode of operation, the faster memory bus is not acquired until the
peripheral has finished or almost finished transferring its data. A FIFO can be used for the peripheral write
operations as well, which creates a need for bidirectional FIFOs as shown in Figure 8.
6-28
QUALITY SEMICONDUCTOR INC.
AN-02: FIFOs as High-Speed Data Queues for Systems
SYSTEM BUS
ADDRESS, DATA, CONTROL
PERIPHERAL
DEVICE
Figure 8. Using the FIFO with a High-speed CPU,
DMA Controller and a Slow Peripheral
rectional
Bidirectional FIFOs also have applications for interfacing between the CPU local bus and an external
system bus. The high speed access times of 20 ns and a data set up time of 1 0 ns in
20 ns speed -grade FIFOs make them ideally suited for high-performance DSP devices such as the Tl
32025, as shown in Figure 9. Different speed grades (25 ns, 35 ns, 50 ns, 80 ns and 120 ns) are also
available. ^ g stom&xa oom i mlotj rftonai milt tUmu iuli AJ toiiiliUn itiU i?
QUALITY SEMICONDUCTOR INC.
6-29
AN-02: FIFOs as High-Speed Data Queues for Systems
SYSTEM
TMS32025
or
68030
INTERRUPTS
ADDRESS,
CONTROLS
R/W
CONTROLS
Figure 9. Bidirectional FIFOs in High-Speed Applications
Image Processing Systems
FIFOs are used in image processing systems for interfacing to A/D converters and for providing data in a
sequence to computational units. In high-speed acquisition systems, data is acquired by an A/D
converter at high frequency and processed by a slower microprocessor-based system. FIFOs can capture
the data at speeds up to 33 MHz and the microprocessor can read the data at a slower frequency. Figure
1 0 shows a system with a 1 0-bit or 1 2-bit A/D in the front-end. Since FIFOs can be expanded in width, two
FIFOs are used. The flag indicator from either FIFO can be used.
MICROPROCESSOR
ANAUOG
INPUT
A/D
FIFO
512-20K
DATA
DATA
►
deep
►
►
FLAGS
INTERRUPTS
10-bit
►
or
12-bit O/P
Figure 10. FD
FIFOs with minimal logic can create fixed-length delay times. For example, if you need a delay line of 1 178
time slots, you can program a counter with 1 1 78 and decrement it with each write clock edge. After the
6-30
AN-02: FIFOs as High-Speed Data Queues for Systems
count is zeroed, the read clock is enabled by the write clock signa
the system has reads and writes off the same clock. The sche
diagram; more logic must be added depending on the application.
illows a programmable delay and
vn in Figure 11 is a conceptual
The TC can be ANDed with the CLK signal to create the Read signal to the FIFO or the read logic can be
user defined.
Figure 1 1 . A Programmable Delay Using FIFOs
FIFOs configured in the above manner can be combined with similarly configured FIFOs in image
processing applications. A screen of data is shown in Figure 12. A typical operation may be the
computation of a threshold function in which a matrix multiply of a 3x3 pixel arrangement with another
matrix may be required. Assume that each row of the screen can be stored in a FIFO. If the row is not
representable as a power of 2, counters can be added to create fixed-length delay lines to create the
appropriate screen width. In a typical application, a screen width of 1 024 pixels d ,c2,c3 are received at a
certain time. Pixels b1 , b2, b3 are received 1 024 time delays later, and pixels a1 , a2, a3 are received yet
another 1 024 time delays later. The rows of the screen can be stored in three FIFO as shown in Figure 12.
The outputs of these FIFO can be connected to numbercrunching elements to compute the required
matrix multiply operation.
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■
■
!
QUALITY SEMICONDUCTOR INC.
6-31
AN-02: FIFOs as High-Speed Data Queues for Systems
■
-4 1
= Depth of FIFO ^
The nine outlined squares are used for computing a threshold function at a
particular instance of time. The value of the pixels can be stored in FIFOs,
where one FIFO is used per row.
Incoming Data
To
Numbercrunching
unit
Figure 12. FIFOs in Image Processing Systems
F|fq Retransmit Applications in Pata Communications
The FIFO retransmit pin enables resetting the read pointer to zero without affecting the write pointer. The
retransmit feature can be used in data communication applications where data is transmitted but an error
was detected externally and the packet of data must be retransmitted. This can be done by asserting the
retransmit signal and by sending the packet of data all over again. The retransmit feature is executed as
follows: the FIFO is reset; the number of words written in the FIFO are less than the depth of the FIFO;
the words are read and can be re-read as shown in the first level of Figure 13. If subsequent writes occur
and the write pointer wraps around the zero mark, if the retransmit signal is then asserted, the user will
only get the words from pointer location zero to the location of the write pointer. This is shown in the lower
level of Figure 13.
6-32
QUALITY SEMICONDUCTOR INC.
AN-02: FIFOs as High-Speed Data Queues for Systems
FIFOs is reset Data is written All data is read The retransmit
pin is asserted
allowing data to
be re-read.
m
1 — A — i
<-
I J
B 1
Data is written
Further reads
and writes
Further
writes
If blocks A and B
are read and then
retransmit is
asserted, then only
block B can be re-read
as the read pointer resets
to zero during retransmit.
Note: The arrows on the left side indicate the write pointer and the ones on the right indicate the read
pointer. The upper level diagrams are a normal retransmit and the lower level indicate a limitation of the
retransmit operation.
Figure 13. Retransmit Operations
Conclusion
FIFOs are useful as data queues to match data rates in computer systems. With cycle times of 25 nsec,
newer applications are available in graphics and DSP systems and in data communication systems. With
fast flag access times, external timings are relaxed by using Quality Semiconductor FIFOs. These FIFOs
provide better results in high reliability systems.due to the 6-transistor cell design.
QUALITY SEMICONDUCTOR INC. 6-33
'
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■
QUALITY SEMICONDUCTOR INC.
AN-03: The 6-T SRAM Cell and Its Advantages
—————— -— ^^^^^-Ba--
Q
The 6-Transistor
SRAM Cell
and Its Advantages
by
David Wyland
Application
Note
AN-03
Data in RAM memories is stored in bit cells, one for each bit in the memory. For example, a 1 6Kx4 SRAM
stores its 65536 bits in 65536 separate bit cells. High speed CMOS SRAM bit cells come in two types,
four-transistor (4T) and six-transistor (6T). The 4T cell is the smaller of the two, while the 6T cell has higher
performance. New developments in cell design allow the 6T cell to be made nearly the same size as the
4T cell. In this application note, we will examine the differences between the 4T and 6T cell and the
advantages and disadvantages of each.
The four-transistor and six-transistor cells are so named because they use four and six transistors
respectively in the cell design. Figure 1 shows circuit diagrams of the 4T and 6T cells in an SRAM design.
The cells and their support circuitry are similar except that the 4T cell uses a pair of resistors for cell pull-up,
while the 6T cell uses P-channel transistors for this purpose.
Vcc
Read Sense Amp
Vcc
Vcc
Read Sense Amp
Vcc
Vcc Vcc
Q5
Q3
n r
1
rtf°6S
1=
to
Q4
Word Line
I — | C 011 010 ■ l — 1
V Write 0 Write 1 V
f 1 ""V'
V write 0 Write 1 V
Figure 1 ; 4T and 6T SRAM Cells
QUALITY SEMICONDUCTOR INC.
6-35
=
AN-03: The 6-T SRAM Cell and Its Advantages
SRAM Operation with 4T and ST Cells
■
Data in the SRAM cells shown in Figure 1 is stored in the cross coupled latch formed by Q1 and Q2. A
zero is stored when Q1 is on and Q2 off; a one is stored when Q2 is on and Q1 is off.
To read or write data to the cell, the bits in a word are selected by taking the word line high. This turns on
the select transistors, Q3 and 04, and connects Q1 and Q2 to the bit lines, Bit Line and Bit Line. When
the select transistors are on, Bit Line or Bit Line is taken low by Q3 or 04 if a zero or one is stored,
respectively. The sense amplifier detects which line has been taken low and generates a one or zero
according to the difference in voltage between the bit lines.
A sense amplifier is used to increase speed. Q3 and 04 are intentionally made weak so that when they
are turned on, only a small voltage drop appears across R1 or R2, and very little voltage develops across
Q1 or Q2, respectively. This allows R1 and R2 to be made small, reducing the time constant and
corresponding settling time for the voltage developed across them. The sense amplifier amplifies the
voltage developed to a full logic level. The sense amplifier also provides an earlier indication of the logic
level because the full, final voltage does not need to be developed across R1 or R2 before the sense
amplifier can tell a one from a zero.
Data is written into the cell by turning on Q1 0 or Q11 when the word has been selected. This brings Bit
Line or Bit Line low, respectively. Q3, Q4, Q10 and Q1 1 are made strong enough relative to the current
capability of R5 and R6 or Q5 and Q6 to allow Q1 0 and Q1 1 to directly drive the cell nodes of Q1 and Q2.
Turning on Q1 0 will write a zero by bringing the drain of Q1 and the gate of Q2 low. Q2 will be turned off,
and R2 will pull the drain of Q2 and the Gate of Q1 high. Q1 will be turned on, helping to hold the gate of
Q2 low. When the word line is turned off, the latch will remain in the zero state with Q1 on. R6 will hold the
gate of Q1 high against any leakage in Q2.
Turning on Q1 1 will write a one by bringing the drain of Q2 and the gate of Q1 low. Q1 will be turned off,
and R1 will pull the drain of Q1 and the Gate of Q2 high. Q2 will be turned on, helping to hold the gate of
Q1 low. When the word line is turned off, the latch will remain in the one state with Q2 on. R5 will hold the
gate of Q2 high against any leakage in Q1 .
The Advantage of the 4T Cell Over the 6T Cell
The important advantage of the 4T cell over the 6T cell is that the 4T cell is smaller than the 6T cell. The 4T
cell is approximately half the size of a conventional 6T cell. This results in a smaller die size and somewhat
higher performance because a small die size generally has less capacitance. Thus, the 4T cell has been
preferred for high speed SRAMs for feature sizes down to approximately 1 uM.
This size advantage of the 4T is paid for by a variety of second order problems associated with the 4T cell
that are not present in the 6T cell. Although the 4T cell is smaller, the 6T cell has better electrical
characteristics. The problems with the 4T cell are aggravated as the cell sizes are made smaller: i.e., the 4T
cell works well at 1 6K bits but does not work as well at 1 megabit. The size advantage of the 4T cell is also
disappearing due to new design and process techniques. It is now possible to build 6T cells
approximately the same size as their 4T counterparts. This promises to change the way SRAMs are
designed.
6-36 QUALITY SEMICONDUCTOR INC.
AN-03: The 6-T SRAM Cell and Its Advantages
The Advantages of the 6T Cell Over the 4T Cell
The 6T cell has several known advantages over the 4T. The 6T cell has a lower standby power than the 4T
because the 4T has pull-up resistors in each cell drawing current, while the 6T cell has no standby current
other than leakage. At room temperature, the 4T standby current may be microamperes, while the 6T
current can be nanoamps. This is useful in battery powered equipment.
There are several other areas where the 6T cell has definite advantages: lack of static hold problems, good
radiation hardening characteristics, ability to scale to higher densities, and better alpha particle immunity.
These problems will be discussed in turn.
Static Hold In 4T and 6T Cells
Static hold refers to the ability of a device to retain information. It is defined negatively: an SRAM with a
static hold problem "forgets" data if left sitting for a long enough time without use.
Static hold problems occur in 4T cell SRAMs because of leakage. The pull-up resistors in the 4T cell, R5
and R6, are very large, 100 glgohm being typical at room temperature. As a result, they can sustain a
leakage current in the off device of Q1 or Q2 of less than 50 picoamperes at room temperature.
Static hold problems occur in 4T SRAM cells because of subthreshold leakage in the Q1 -04 transistors.
Subthreshold leakage is actually transistor action. When the gates of Q1 -04 are at zero volts, significantly
below threshold, there is still some transistor action, albeit very small. If a plot of current versus gate
voltage is made, the current through these devices does not cut off immediately at threshold but declines
exponentially with gate voltage. Even though the gate voltage may be zero, there can still be some
current flowing. It can be eliminated only by taking the gate voltage significantly below the threshold
voltage.
The typical static hold problem with a 4T cell occurs at cold temperature rather than hot. The subthreshold
leakage current is a function of transistor geometry and doping profiles, and is not a strong function of
temperature. The R5/R6 pull up resistors are made from high resistivity polysilicon, which has a strong
temperature coefficient, with the resistance going up as the temperature goes down. The current
capability of these resistors therefore decreases rapidly with decreasing temperature. At cold
temperatures, the subthreshold leakage may exceed the current that can be supplied by R5/R6 and
cause the cell to become unstable or flip over. At this point, the SRAM has "forgotten" its data.
Static hold problems are expensive to find in terms of test time. Because the leakage is very small
compared to the node capacitances, you typically have to wait one or more seconds for the subthreshold
leakage to drag down one or more nodes. Also, tests must be performed at cold temperatures; you
cannot correlate a static hold problem to room temperature data.
Static hold problems in 4T cell SRAMs usually occur because of variations in the manufacturing process. If
the resistivity of the polysilicon gets too high on a lot or varies significantly across a wafer, you can have
static hold problems. These can be overlooked because the part appears to work at room temperature
and for normal test times of a few milliseconds per read/write pass through the RAM.
The 6T cell has no static hold problems. The Q5/Q6 pull-up transistors are capable of supplying orders of
magnitude more current, microamperes instead of picoamperes, compared to the 4T cell. As a result,
subthreshold leakage cannot cause a static hold problem.
—
QUALITY SEMICONDUCTOR INC.
6-37
AN-03: The 6-T SRAM Cell and Its Advantages
Radiation Hardening Capability ot 4T and 6T Cells
Gamma radiation affects 4T cells more than 6T cells. Typical failure dose numbers for untreated SRAMs
are on the order of 1 0K rads for 4T devices and 50-1 OOK rads for 6T devices. Gamma radiation is
commonly encountered in spacecraft and satellites, being solar radiation without benefit of shielding by
the atmosphere.
Gamma radiation changes the threshold of devices. It also causes additional leakage currents because of
surface effects at the silicon/Si02 interface. Change in threshold voltage is generally in the direction to
increase subthreshold leakage in N-Channel devices. Because the 4T cell is sensitive to leakage in the
cell due to the low leakage tolerance of the R5/R6 pull up resistors, 4T cell RAMs have relatively low
radiation tolerance. Absorbing a large enough dose of radiation results in static hold problems. The 6T
cell fares much better because it lacks the resistors which cause static hold problems.
High Density Scaling Capability of 47 and 6T Cei's,
The 6T cell looks increasingly better than the 4T as the cell sizes are made smaller. This is important as
SRAMs go to ever higher densities and smaller geometries.
As cells are "shrunk" ,i.e., made geometrically smaller as though increased production equipment
resolution, a first approximation would say that most electrical characteristics remain the same. In a
geometric shrink, the resistance of R5/R6 in the 4T cell should remain constant if the ohms/square remain
the same because the number of squares is the same in a geometrical shrink. However, as the cell is
made smaller, this does not hold true.
As you shrink the X and Y dimensions, you must also shrink the Z dimension, the thickness of the
polysilicon. This increases the ohms/square, increasing the value of the resistor. Not only does the
ohms/square number increase, but it increases non-linearly. A small decrease in polysilicon thickness can
result in a large increase in the ohms/square, significantly above the linear increase with decreasing
thickness one would expect. This makes the polysilicon resistivity harder to control.
As you shrink the absolute distances involved, the polysilicon begins to be affected by the silicon it
contacts. There is diffusion of dopant from the substrate into the polysilicon. This causes two problems.
Diffusion of dopant into the relatively undoped polysilicon will reduce its resistivity in a relatively
uncontrolled manner. It will also create the conditions for breakdown, or punch-through, of the resistor at
normal operating voltages, giving high and erratic currents in the cell.
Another problem associated with shrinking the 4T cell is that the subthreshold leakages of the devices
increase in absolute terms as they are made smaller. Increasing subthreshold leakage coupled with higher
and more poorly controlled resistor values is a recipe for static hold problems.
The net result of these mechanisms is that shrinking the 4T cell causes manufacturing problems related to
control of the polysilicon load resistors, R5/R6. These manufacturing problems show up as yield loss and
reliability problems such as static hold.
The 6T cell does not have these problems because it does not use polysilicon load resistors. The shrink
of the 6T cell is an exercise in shrinking the geometry of the transistors themselves, a better known and
controlled operation.
•
6-38
QUALITY SEMICONDUCTOR INC.
AN-03: The 6-T SRAM Cell and Its Advantages
Alpha Particle Soft Error Performance of 4T and 6T Cells
The 6T cell has better alpha particle error characteristics than the 4T cell. This problem is, again, related to
the resistor pull-up in the 4T cell. An alpha particle is a charged helium nucleus which has a high energy
level and can penetrate significant distances through solid matter, such as an IC package or piece of
silicon. Alpha particles are generated by radioactive decay. Every package, plastic or ceramic, has trace
elements of radioisotopes which generate alpha particles as they decay. Alpha particles can also be
generated from other materials in and around the equipment where the SRAM is installed.
When an alpha particle passes through a piece of silicon, it leaves a trail of ionized particles, i.e. hole-
electron pairs. If the particle passes through the depletion region of a SRAM bit cell transistor, it can cause
a transient current in that transistor. The particle passes through very quickly, on the order of 100
picoseconds. If this happens to Q1 , it will have a momentary pulse of drain current corresponding to the
charge generated by the particle. This will immediately discharge the capacitance at node A, the
capacitance associated with the drain of Q1 and Q3 and the gate of Q2. This looks very much like writing a
zero to the cell. If the charge generated by the particle is large enough, this is what happens.
There will be some alpha particles (or combinations of particles) which generate sufficient charge to flip the
cell, i.e. do a false write. This means that the alpha particle problem cannot be absolutely eliminated, only
reduced. The alpha particle problem is therefore defined as a soft error rate probability per alpha particle,
or alternatively a soft error rate as a function of alpha particle emission rate.
When an alpha particle has discharged the stray capacitances associated with Q1 , the cell must now
recover. In the 4T cell, this means that R6 must recharge the capacitance of node A. Although the
capacitance at this node is small (50 f F typical) the pull up resistor is so large (1 00 g£i) that the time
constant of this node is in milliseconds. During this interval, the cell is in an internally metastable state. If
the cell is selected, the pull up resistors now become R1/R2, a much smaller value. However, the node
must still stabilize. The metastability still exists, but with a shorter resolution time. Although the values of
R1/R2 are small, the capacitance of the bit lines is relatively large. The result is that the metastable settling
time may be significant with respect to the access time of the device.
Because of the metastable action of the 4T cell, alpha particle impact can result in lengthened access
times as well as simple flipped cells. The lengthened access times export metastability to the next system
interface, resulting in soft errors due to transiently exceeding timing margins. This increases the effective
soft error rate of the 4T cell.
The 6T cell does not have this metastability problem, in a practical sense. In the 6T cell, the Q5/Q6 pull up
transistor results in a much lower effective time constant, on the order of a few nanoseconds rather than a
few milliseconds. As a result, the probability of a metastable stretchout of the access time is very small.
The alpha particle would have to hit during the access itself to cause this to happen. This reduces the
probability of this type of error by approximately the ratio of the two time constants, several orders of
magnitude.
Conclusion
The 4T cell was preferred for fast RAM designs below 64K bits and using 1 .2 u.M or larger lithography
because of its smaller cell size. Its problems were born because of the benefits of yield and speed that
small cell size gave. New techniques have allowed the 6T cell to approach the 4T cell in relative size,
eliminating the need to suffer the tradeoffs of the 4T cell. This has happened just in time because as
SRAM densities progress beyond 256K and lithography resolution drops below 1 .0 uM, the 6T cell
becomes a necessity for fast, high yield SRAM design.
QUALITY SEMICONDUCTOR INC.
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6-39
i
AN-03: The 6-T SRAM Cell and Its Advantages
■
6-40 QUALITY SEMICONDUCTOR INC.
AN-04: SRAMs and Bus Contention
Q
High Speed SRAMs
and Bus Contention Issues
by
Suneel Rajpal
Application
Note
AN-04
Memory devices are mainly used in bus-oriented systems. Fast SRAMs with common I/O data may
encounter bus contention while switching from read operations to write operations and vice versa. Figure
2-1 shows a common I/O SRAM connected to an external driver. Figure 2-2 shows an SRAM output being
disabled due to a write operation, and the system placing data on the RAM data inputs. Bus contention
can occur when two devices drive the bus simultaneously. The data is in high impedance tWHZ ns after
the write line goes low. This can directly affect the write pulse width minimum specification which is the
sum of tWHZ and tDS, the data setup time.
W
ON
OE
EXTERNAL
BUS DRIVER
-fcr5
7*
ON
OFF
SRAM WITH COMMON I/O
Figure 2-1. Possible Data Contention
in SRAM wit
h Common I/O
QUALITY SEMICONDUCTOR INC.
6-41
AN-04: SRAMs and Bus Contention
W ^\
Hi-Z
RAM O/P
f
EXT. DRIVER O/P
Hi-Z/
BUS LINE
BUS CONTENTION
Note: CS is asserted for this mode
Figure 2-2. Bus Contention Upon SRAM Disable/external Driver Enable Overlap
Figure 2-3 shows another way to eliminate bus contention, by disabling the data inputs to the SRAM prior
to enabling the output.
t
RAM O/P
V
WHZ
/
EXT. DRIVER O/P
Hi-Z
f
BUS LINE
/
Note: CS is asserted for this mode
Figure 2-3. Input Driver Disabled Prior to Disabling RAM Output
6-42
QUALITY SEMICONDUCTOR INC.
AN-04: SRAMs and Bus Contention
Figure 2-4 shows the chip select being used to avoid bus contention. The chip is deselected before the
write operation begins. The write signal is asserted tCHZ ns after the chip select is deasserted. There is no
disadvantage from a speed viewpoint because the write pulse width in this case is measured from the
falling edge of C5 to the rising edge ofCS or WE. However bus contention is eliminated.
cs
w
/
\
\
RAM OUTPUT ^_
Hi-Z
INPUT DRIVER
BUS LINE
Hi-Z
CHZ
Figure 2-4. Avoiding Bus Contention by Using CS
QUALITY SEMICONDUCTOR INC.
AN-04: SRAMs and Bus Contention
Another way to avoid contention in the common I/O devices is to use the output enable control to keep
the outputs in high impedance. This is shown in figure 2-5. Quality Semiconductor's 16Kx4 SRAMs have
output enables in the QS8886 and QS8885. These are suitable building blocks for cache memory and
high-speed add-on memories for applications with zero wait state operations.
OE
W
RAM OUTPUT
\
Hi-Z
t OHZ
Hi-Z
INPUT DRIVER
BUS LINE
X
Figure 2-5. Avoiding Bus Contention by Using Output Enable in the QS8885/6
Devices with separate I/O do not have bus contention problems because dedicated ports are assigned for
the input and output. QS8881/2 are devices with separate I/O. These are useful in implementing control
stores for bit-slice and DSP systems, and for data caches. These applications are covered in Chapter 3.
6-44
QUALITY SEMICONDUCTOR INC.
AN-04: SRAMs and Bus Contention
HIGH-SPEED DESIGN ISSUES AND BOARD LAYOUT CONSIDERATIONS
Microprocessors operate at speeds of 33 MHz and RISC-based processors operate at 40 MHz in "in-
compatible systems. This places a greater challenge on SRAM circuit designers with the requirements for
access times, data set up times and output enable/disable times. Another consideration is the
characteristic of high-speed buses.
High-speed microprocessor buses tend to operate in harsh, noisy environments and sometimes the
buses are unterminated. Unterminated bus lines can receive and radiate Electromagnetic Interference
(EMI) because they act like antennas. The best way to reduce this EMI is to ensure that the each bus line is
terminated with a low-impedance load that is a pull-up or pull-down resistor.
If the value of the termination resistor is equal to the value of the characteristic impedance of the bus line, it
provides the best incident switching and it minimizes the amount of reflection. The smaller the resistor, the
greater the power consumption. If the resistor is too small, its value can approach the source impedance
value of the transmitting device, leading to a noise margin degradation on the receiving device. A large
resistor value, typically between 1KQ and 10 K£2, can be selected after experimentation.
Another consideration is the ground bounce current. Due to fast switching times and high current
switching, the level of the on-chip ground may change from the external ground as the device charges
and discharges. The on-chip ground voltage is affected by the inductive coupling and changing current.
Since 8-bit SRAM devices can have all eight outputs switching, there is a possibility of an even greater
ground bounce effect. Spurious noise spikes on the power lines can affect the data contents of the
device and also affect neighboring devices' power supplies. Circuit designers have developed circuitry
that controls the rise and fall time to minimize undershoot, overshoot and ringing. This is inherently why 8-
bit SRAM devices are slower than 4-bit SRAM devices for the same density.
Noise can be induced into SRAM devices by inadequate power supply feeds and power supply
decoupling. Ground planes should be used extensively to minimize resistances and inductances.
Otherwise, Vcc or ground bounce will occur. Typically, the resistance should be less than 0.1ft. A
multilayer board with at least one ground plane is recommended. High-quality decoupling capacitors wilh
values between .01 to .1 u.F must be located near the power pins. A large capacitor of about 1 u.F must be
used on each Vcc line to provide for current surges. If the devices are socketed, sockets with gold-plated
copper contacts containing built-in decoupling capacitors are recommended.
■
QUALITY SEMICONDUCTOR INC.
6-45
AN-04: SRAMs and Bus Contention
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QUALITY SEMICONDUCTOR INC.
AN-05: High Speed SRAM Applications
Q
High Speed SRAMs Application
in Cache and Note
Bit Slice Applications AN 05
by Suneel Rajpal
Introduction
This application note deals with applications requiring high-speed RAMs for caches, modifiable
storage and control stores for CISC-, RISC- and bit-slice-based systems. There are different
requirements for primary and secondary caches. Quality Semiconductor devices extend from
4Kx4 cache tag RAMs to 16Kx4 cache tag RAMs and 16Kx4 SRAM. Higher density products,
such as 8Kx18, 8Kx16, 32Kx8 and 64Kx4 are also in development.
SRAM requirements for Cache Memory Implementations
Cache memories are prevalent in high-end CPU designs. They increase system performance by
reducing main memory accesses. A cache is a small high-speed memory that is placed between a
CPU and a larger, slower main memory. The cache keeps a copy of main memory data. When the
CPU does a memory operation it looks up a cache tag RAM which determines if the requested
word is present in the cache data memory. If the data is present in the cache, the main memory
does not have to be accessed on read operations. If not, a main memory cycle is initiated and the
cache data and tag RAM are updated.
A direct mapped cache is implemented by storing main memory data in only one possible location
of the cache. In two-way set associative and Multi-way set associative schemes, data from main
memory can be in more than one bank, thereby changing the hit rate of that particular cache
organization.
Some of the features required in implementing cache data and cache tag RAMs are high speed
accesses, very fast enable and disable times and short write pulse widths. Quality Semiconductor
SRAMs are to be ideal for cache implemetations.
The high speed versions of the Intel 80386 CPU enhance their performance with an external
cache. There are two popular approaches: (1) a cache controller-based design, such as the Intel
82385 that contains the tag portion and generates the controls for the cache data RAM, or (2) a
cache controller that is user-defined, built of discrete logic and PALs, for which both tag and data
RAM have to be added externally.
Figure 3-1 shows an Intel 82385 cache controller that accesses a 32-Kbyte cache. The external
cache can be organized as a 2-way set associative or direct mapped. Figure 3-1 shows the 80386
with the 82385, and the cache data RAM in this application is without a buffer. A QSFCT373/A
device that stores the 80386 local address is shown .
QUALITY SEMICONDUCTOR INC.
6-47
80386
CPU
DATA
CONTROLS
t t
ADDRESS
CALEN__^ QSFCT373A
82385
CWEA
CWEB
COEA
COEB
SRAM
8Kx32
or
2x8Kx32*
2x16Kx32*
CS0-CS3
* These configurations are possible with very little external logic
and can be done using QS8816 or QS8817, which are 2x4Kx16 SRAMs
with on-chip latches.
Figure 3-1 . The Intel 80386 with 82385 Cache C
The critical path of the SRAM is estimated as follows for a 33 MHz CPU. The 82385 controller
contains the cache tag RAMs that determine if a cache hit occurred (implying a match condition
existed in the tag RAMs). On a hit condition the outputs of the data SRAM are enabled by the
/COE signal from the 82385. The data accessed from the SRAM has to be valid before the setup
time of the 80386 processor. The SRAM requirements are computed as follows:
6-48
QUALITY SEMICONDUCTOR INC.
Appllcdt ions
Read Cycles
2xCLK2 period-t25b(82385-/COE delay)-SRAM(/OE to data valid)-t21 (80386 data setup)£0
30-15-tOE-5>0
t OE (output enable to valid data) of the SRAM must be < 1 0 ns
4xCLK2-t21b(CALEN valid delay)-tpd Latch to output (QS FCT373/A)-SRAM addrs to data
t21 (80386 data setup)>0
60-20-tpd(FCT373/A)- SRAM(tAA)-5>0
tpd(QSFCT373/FCT373A LE to Output delay) + SRAM adrs to data delay£35 ns
Cache Read Cycle followed by a Write
Data turn-off=t25c (82385 /COE delay) + SRAM Output Disable tOHZ
Dataturn-off=12+tOHZ
Data turn-on= CLK2 period+t12 80386Write data valid delay (min)
Data Turn-on= 1 5+7
Therefore, tOHZ (output disable time) <9 ns to avoid contention (giving a 1 ns margin).
The QS8816 2x4Kx16 SRAMs will have adequate margin to meet the requirements of the above
timings. In the above timings, when the QS881 6 is used, the FCT373 is eliminated from the
access time computations, as the 8816 has an on-chip latch for address storage. You can also
calculate the values for write cycles. However, read timings require faster specifications.
Figure 3-2 shows the cache data RAM being buffered with QSFCT245 devices. In this
configuration, the read followed by a write is not as critical as the previous non-buffered case
because the buffer disable time is much faster than an SRAM disable time.
QUALITY SEMICONDUCTOR INC.
6-49
AN-05: High Speed SRAM Applications
80386
CPU
CONTROLS
1 r u
DATA
COEA
ADDRESS COEB
CALEN
CT/R
QSFCT245A
82385
CWEA
CWEB
QSFCT373A
!
r
CS0-CS3
SRAM
8Kx32
or
2x8Kx32*
2x16Kx32*
T
* These configurations are possible by using QS8816/7
2x4Kx16SRAMs
Figure 3-2 The 80386 with 82385 Cache Controller and External Buffers
6-50
QUALITY SEMICONDUCTOR INC.
AN-05: High Speed SRAM Applications
The critical path tor read operations is estimated as follows: the 82385 provides the control signals
for the QSFCT245 buffers that enable the data to the 80386 bus before the required set up time.
2xCLK2 period -t25b (82385-CDE delay) -tpd (OE to A delay) -t21 (80386 data setup) 2: 0
30 -15-tpd(QSFCT245)-5>0
tpd(DFto A delays 0 ns
4xCLK- 121 b (82385-CALEN delay) - tpd QS FCT373A( LE to output) -
SRAM (address to data delay) -tpd QSFCT245A(A to B)- 121 80386
data set up>0
60 - 20 - 8.5-SRAM( tAA)^.6 -5>0
SRAM(tAA) <21 ns
The SRAM access times are easily satisfied by QS SRAM devices. If external latches are not
needed, the required access time of the latched SRAMs should be less than 29.5 ns. The
estimated worst case access time of the latched SRAMs, 881 6/7, is 20 ns.
11 r-
■
i-t-
-1
6-51
AN-05: High Speed SRAM Applications
Intel 386 CPU Non-82385 Applications
Customized cache controller designers use separate cache tag RAMs and cache data RAMs.
Typically a 4K, 8K or 1 6K deep tag RAM is used. The data RAM can be 8K or 1 6K deep. Figure 3-
3 shows a typical application where a l6K-deep tag RAM and l6K-deep data RAM are used.
ALTERNATE TAG
IMPLEMENTATION
80386
DATA
CONTROLS
ADRS
1
5 16Kx4 Cache
Tag RAMs
FCT244A
or ?73A
4
TAG FUNCTION
5 16Kx4
SRAM
I
FCT521 Bs
► F
PAL
and
OTHER
LOGIC
MATCH
J
I
DATA
16Kx32 SRAM
for
CACHE DATA RAM
WE
Match 0-4
The QS 8883 cache tag RAM has an on-chip comparator
that allows address to match times of 12 ns
Figure 3-3 The 80386 with an External Direct Mapped Cache
On memory accesses it can be determined if the requested word is present in the cache tag RAM
by examining the match output. The assertion of the match signal indicates that the previously
stored tags are equal to the current access, and on read requests the main memory does not have
to be accessed. On processor writes, main memory is updated on every cycle if a write-through
scheme is implemented. A dirty bit is set on the write-back scheme and the main memory is
updated later.
The critical timing in these applications are the address to match (maximum) specification and the
write pulse width (minimum) specification. The first critical parameter is directly used in the path to
turn on the QSFCT245A device during read hits. The second parameter is based on the write
miss operation, and an entry may have to be invalidated in the cache tag RAM. This assumes that
on write operations the data is always updated in the cache data RAMs, and if a cache miss
6-52
QUALITY SEMICONDUCTOR INC.
AN-05: High Speed SRAM Applications
occurred, the corresponding entry in the tag RAM is invalidated. This update technique
generates a particular critical path, and the data setup time and the write pulse widths are key
parameters for no wait state operations. The QS8883 cache tag RAM devices are ideal for
building cache tag and data RAMs and eliminating wait states. The QS8883 cache tag RAM
combines the comparator inside the device so that the address to match time is only 12 ns.
ntel i
The Intel 804
an External Cache
The Intel 80486 has an on-board 8 Kbyte cache, and its performance can be enhanced with an
external second-level cache. Figure 3-4 shows an 80486 CPU with an external, 2-way set-
associative 64 Kbyte cache.
i486 CPU
ADDRESS
Cache Tag RAM
2x4Kx16
QS8813
MATCH
PAL
Glue Logic
•
1
r
2x16Kx36
4 x QS8818
BANKO
and BANK 1
OE0.OE1
TA
ies the tag RAM access time plus the output enable to data valid
specification of the cache data RAM
Figure 3-4. The Intel 486 with an External Cache
The external memory used in 80486 applications must support burst transfers. The first word is
accessed in two 80486 clock cycles and the subsequent three words are accessed in one clock
cycle each. The external system indicates that it can present valid data by asserting the BRDY#
signal to the processor. If the BRDY# is not asserted at the appropriate rising clock edge, then a
wait state is inserted. The 80486 address signals are switching during burst mode operations.
However, these cannot be used to access the SRAMs as there will be insufficient time to execute
the burst without adding wait states. The high-speed burst access can be accomplished by
enabling the outputs on one of the two banks and also by toggling the least significant address
bit. This is explained in the timing diagram shown in Figure 3-5.
QUALITY SEMICONDUCTOR INC.
6-53
AN-05: High Speed SRAM Applications
CLK
—
AO
DATA
Enable AO
Bank 0,1
X
Read
Bank 0
Enable AO
Bank 0
X
Enable AO
Bank 1
X
X
X
X
Read
Read
Bank 0
Read
Bank 1
SRAM ADDRESSES
A13-A1 ARE
LATCHED AND
DO NOT CHANGE
DURING THE BURST
If A1 is a 1 initially then the first data word is accessed
from Bank 1 . If A1 is 0 initially then the first word is accessed
from bank 0. AO is stored in a latch and this is done in a clock cycle
prior to the required data word.
Figure 3-5 Burst Cycle Timings
In analyzing the critical paths for zero wait state performance, two specifications are important.
These are the cache tag RAM access time and the output enable time for the cache data RAMs.
This is apparent from the following equation:
tWBV ncs of Nlisrie jucfi v. •,■ • i acs&is MA>i ../il aebytoni nyiq teoi'io 5>r1'r
Address Valid (t6-80486 spec)+ Tag ram Access + PAL delay + Output Enable Time(Cache data
RAM) + data setup time (t22-80486 spec) + derating< 60 ns
Inserting t6=16 ns, t22=5 ns, PAL delay= 7.5 ns, derating = 2ns,
Tag RAM access address to match delay + Output Enable to valid data(Cache Data RAM) <, 29.5
ns
As one designs with higher speed processors, there is increased demand for faster access times,
faster enable and disable times, and integration of latches or self-timed write operations.
Quality Semiconductor, Inc. makes high speed logic devices such as latches and registers. The
SRAMs have fast enable and disable times as well. This allows 2-1 -2 cycles (two cycles for the first
read, one cycle each for the next three reads, and two cycles for a write) for the 80486 processor.
The 8Kx18 SRAMs also has on-chip counters to support burst mode operations transferring four
words to the CPU . Quality Semiconductor is also defining SRAMs and modules that are
application-specific for Intel microprocessors.
6-54
AN-05: High Speed SRAM Applications
The MIPS RISC processor
The MIPS RISC processor requires external caches for instructions and data. The processor
provides the necessary control signals to latch the instruction and data address, and also stores
the corresponding data. Figure 3-6 shows the bus operations during Phases 1 and 2 of the clock.
Figure 3-6 shows the ping-pong effect of the processor caches. Every cycle, either the
instruction or data cache are accessed. On the following cycle, the other cache is accessed.
ADDRESS
1 . Accesses during Phase 1
2. Accesses during Phase 2
Figure 3-6 The Instruction and Data cache for the MIPS RISC Processor
Bus contention is possible, and this demands fast enable and disable times for any selected
SRAM. Also, if you analyze the 25 MHz RISC processor specification, the access times of the
SRAM have to be 19 ns or less for proper operation, and the data setup time must be less than 1 1
ns. The SRAMs must have zero hold time for both address and data from the end of write. The
SRAM devices made by Quality Semiconductor, Inc. either meet or exceed the requirements for
the MIPS RISC processor at 33 MHz. All of the key requirements such as access times, output
enable times and data set specifications are met by the 16Kx4 SRAMs made by Quality
Semiconductor.
QUALITY SEMICONDUCTOR INC.
6-55
AN-05: High Speed SRAM Applications
Bit Slice Processors
In the high-performance end for controllers and graphics, users often implement their systems
based on bit-slice type machines. This gives a performance edge for certain applications. The
numbercrunching elements can be based on bit slice, gate arrays or discrete elements. However,
the memory portion is always based on high-speed SRAMs and can not be integrated.
Figure 3-7 shows a portion of the implementation with the address sequencer, the pipelined
register and the microinstruction store. The microinstruction store is loaded on power up, and if
SRAMs with common I/O are used, external glue logic is needed. If however, SRAMs with
separate I/O are used, data is stored using one path on powerup and read from a separate path.
Because of this, external buffers are not needed unlike in SRAMs with common I/O. Figures 3-8a
and 3-8b show the microinstruction store implementation using common I/O and separate I/O
SRAMs respectively.
GATE-ARRAY
OR STANDARD
MICROPROGRAM
SEQUENCER
ADDRESS
16KX64
SEPARATE I/O SRAMs
16 QS8881/2
DATA
DATA(LOADED ON
POWER UP)
QSFCT374
Figure 3-7. An Implementation of Microinstruction Store
6-56
QUALITY SEMICONDUCTOR INC.
AN-05: High Speed SRAM Applications
16Kx4
SRAM
16Kx4
SRAM
16Kx4
SRAM
Four Common I/O
16Kx4 SRAMs
t
16Kx4
SRAM
4
FCT245S
^/ ^ Data
Bus
WE
Decoder
To SRAMs
Address
Address
Register
u.P Adrs
Bus
Figure3-8a Implementation of Microinstruction Store Using Common I/O SRAMs
Data in
SRAM
16Kx4
SEP I/O
T
SRAM
16Kx4
SEP I/O
T
Data Out
SRAM
16Kx4
SEP I/O
T
SRAM
16Kx4
SEP I/O
T
One
FCT374
Decoder
Four Separate I/O
16Kx4 SRAMs
To SRAMs-
Rddress
uP Data bus
8
Address
Register
uP Adrs
Bus
Figure 3-8b Implemenation of Microinstruction Store With Separate I/O SRAMs
The SRAMs in this application are in the critical path for the overall cycle times. The applications
generally require 15 ns to 35 ns SRAM access time. Separate I/O RAMs are also used for data
caches and memory mapping SRAMs.
QUALITY SEMICONDUCTOR INC.
6-57
AN-05: High Speed SRAM Applications
81 £
■
6-58
QUALITY SEMICONDUCTOR INC.
Q
ZIP Packages for Logic
Provide High Density
and High Spee
by
David Wyland
Application
Note
AN-06
ZIP packages for high speed logic such as the FCT family provide high packing density in a through-hole
package coupled with superior speed and ground bounce performance. ZIP packages provide density
improvements of almost 2X over DIP packages and 1 .2X over SOIC packages. In addition, they provide a
low ground inductance package which allows high speeds with much lower ground bounce noise than
DIP packages.
ZIP packages are not new. Millions of DRAMs in ZIP packages have been shipped over the last few years.
Recently, however, the advantages of ZIP packages for high speed logic have been discovered. QSI
introduced ZIP packaging for their FCT line of fast TTL logic. In addition to the expected benefits of high
board density in a through hole package, the additional benefits of high speed with superior ground
bounce noise performance were provided.
ZIP For Density
The density comparison between the ZIP, DIP, and SOIC for 20-pin packages can be seen in Figure 1 . A
300 mil DIP requires approximately 400 mils of board width to allow for the pads. This results in a board
area of 0.400 square inches. The equivalent ZIP requires only 200 mils of width but an additional 50 mils
of length to compensate for the staggered leads for a board area of 0.21 square inches. The area ratio is
0.40/0.21 = 1 .90 X improvement in area.
0.300 DIP
id
oj
jo
oi
\o
oj
\o
oi
jo
oj
so
O]
oj
hp
Oi
lo
oi
LP
oj
0.400 W
1.000 L
X
ZIP
)j
<
i
c
i
(
>]
(
>!
(
>j
(
>]
(
(
>!
(
);
SOIC
0.500 W x
0.500 L
with Via Holes
■
0.200 W x
1.050 L
Figure 1: Board Footprints of ZIP, DIP, and SOIC
6-59
AN-06: ZIP Packages for Logic
The SOIC requires only 0.400 by 0.500 for the basic footprint for a total of 0.20 square inches, the same
as the ZIP. In reality, however, via holes are required to communicate between the SOIC leads on the
surface of the board and the internal and back layers of the board. Via holes are provided free in through-
hole DIP and ZIP packages. These holes and their associated pads add another approximately 50 mils to
each side of the 400 mils of width. This results in a footprint of 0.500 by 0.500 for 0.25 square in
The area ratio is 0.25/0.21 = 1 .1 9 X improvement in area of the ZIP over the SOIC.
ZIP For Speed with Low Ground Bounce Noise
ZIP packages are faster than DIP for TTL logic because the ZIP package has lower ground lead
inductance. FCT in ZIP packages with the same pin numbering as the DIP results in the ground lead (pin
1 0 in a 20 pin package) being in the middle of the package, the shortest lead. As a result, the ZIP has less
ground bounce noise than the DIP for the same chip. Figure 2 shows a table which compares FCT244A
drivers in both DIP and ZIP packages.
Parameter
QSI FCT 244A
Units
PDIP
ZIP
Tphl
7 Outputs Switching
4.10
3.90
ns
Volp
(Ground Bounce)
1.56
1.32
Volts
Package Resonance
@ 50 pF/Output
72
120
mHz
Figure 2: Sample Speed and Ground Bounce for QSI FCT244A
In Figure 2, the speed of the 244 is 0.2 ns faster in the ZIP tnan the PDIP, and the ground bounce has
been reduced to 1 .32/1 .56 = 85% of its original value.
The higher speed with lower ground bounce is due to the higher resonant frequency of the ZIP package
for 50 pF loads on the outputs, as shown in Figure 2. (See QSI application note AN-01 "Ground Bounce
Noise in TTL Logic")
Conclusion
ZIP packages for logic provide a method for the designer to improve board space in a through-hole
design, achieving higher density than surface mount packaging while improving the speed and noise
characteristics of his design.
D
AN-07: Resistor Output Logic for High Speed, Low Noise
=
Resistor Output Logic Application
Gives High Speed Note
with Low Noise AN 07
bv
David Wyland
Resistors on the outputs of TTL logic gates have long been used as a technique to damp board reflection
noise. These resistors are typically approximately 25a in value, an empirical value giving the best noise
reduction with minimal loss in speed. With the advent of very high speed TTL logic such as FCT and the
desire to eliminate the board space required by the 25£2 resistor package, there has been a need for logic
parts that incorporate the 25n resistor on the silicon. QSI has responded to this need by introducing the
FCT2000 logic series which provides 25Q resistor output options for virtually all of the devices in the FCT
family. A block diagram of the FCT2000 series is shown in Figure 1 .
Standard FCT244 Resistor Output FCT2244
Figure 1 : 2000 Series Resistor Output Logic
Resistor Output Loolc - Putting the Resistor On the Silicon
The technique of adding resistors to logic was so common in applications such as high speed drivers for
DRAM arrays that logic parts with 25Q outputs were introduced as early as the 1970's in devices such as
the Am2965/66, the 25Q equivalent of the 74S240/244 octal drivers. Since that time, resistor output
parts have been added in piecemeal fashion to a variety of logic parts in a variety of families.
Resistor output parts are quite simple in concept: a 25n resistor is added to each active output. This is
shown in Figure 1 . The advantages of including it in the IC are the savings in board space and the fact that
the composite circuit of IC plus resistor is specified for speed and DC parameters.
The QSI FCT2000 Series: Low Noise Without Loss of Speed
The QSI FCT2000 series is designed to help the designer by providing resistor equivalents of standard
parts which have the same speed ratings. For example, the QSI FCT2000 resistor series parts meet the
same propagation delay specifications as their non-resistor equivalents in the A and non-A speed grades.
This allows a designer to substitute a resistor part for a standard part to reduce system noise without
suffering a speed penalty.
QUALITY SEMICONDUCTOR INC. 6-61
=
AN-07: Resistor Output Logic for High Speed, Low Noise
I
Adding Resistors: Full Speed Without Ground Bounce
Adding resistor outputs can produce dramatic reduction in ground bounce noise and system noise. The
table in Figure 2 compares resistor and non-resistor parts for speed and ground bounce. The resistor part
is 0.30 ns slower than the non-resistor part for the full 50 pF load; however, the ground bounce has been
reduced from 1 .56 volts to 0.80 volts. The resistor ground bounce is 51% of its original value for a 7%
increase in propagation delay.
Parameter
FCT244A
FCT2244A
Units
Tphl
7 Outputs Switching
4.10
4.40
ns
Volp
(Ground Bounce)
1.56
0.80
Volts
Figure 2: Propagation Delay and Ground Bounce for FCT244A vs FCT2244A
Resistor Outputs - Great for AC Loads
Resistor outputs sacrifice DC drive for improved AC noise. Because of the 25ft resistor at the output, a
0.50V Vol can be met at only 12 mA rather than 64 mA. This is a problem only if driving a DC terminated
backplane or transmission line. However, in the common application of driving local, unterminated buses
such as on PC cards, this does not represent a problem. The 64 mA capability is still there to provide the
transient AC drive. The actual requirement is that the speed be there and the noise be gone for real
loads.
Conclusion
Resistor output parts have become a sub-family of logic in the industry. They have come into existence
because of the invention of system designers solving system speed and noise problems. The simple
addition of a resistor to the output of a logic driver can provide dramatic reduction in noise with a small
penalty in speed. Providing the resistor in the logic IC allows its operation with the resistor to be specified
and tested. The result is a powerful and useful tool for the designer to allow the achievement of speed
with reliability.
QUALITY SEMICONDUCTOR INC.
AN-08: QSOP Packages for 32-blt Buses
QSOP Packages Application
Provide High Density Note
in 32-Bit Bus Designs an-os
by
David Wyland
QSOP (Quarter Size SOIC Outline Package) packages for high speed logic such as the FCT family
provide 2.5 to 3 times the packing density of the SOIC packages they replace. QSOPs in bus designs
provide the highest board density, higher than any other package including gate arrays in PQFP. This
results in significant savings in board space and trace delay in 32-bit bus systems common in high speed
RISC and CISC designs.
The QSOP package is a new package based on a standard JEDEC outline. The QSOP is called Quarter
Size because it is approximately one half the length and one half the width of its corresponding SOIC
package. This is done by combining a double density, 25 mil leadframe with a JEDEC standard 14 pin,
150 mil SOIC body. The result is a package that is 340 mils long and 235 mils wide versus 600 mils long
and 406 mils wide for a for a 24 pin, 300 mil SOIC. Although significantly smaller, the QSOP can use the
same handling equipment as the existing 14-pin, 150 mil SOIC. Also, its 25 mil lead spacing poses no
more problems than existing 25 mil QFP packages.
The space savings provided by the QSOP are significant, particularly in 32-bit and 36-bit bus applications.
Table 1 shows the relative area used by QSOP, SOIC, Tl Widebus™ and PQFP gate array solutions to
connecting two 32-bit and 36-bit buses with transceivers. (Note that there is no current 18-bit part
currently available for the 36-bit Widebus™ case. Availability of an 1 8-bit is assumed for comparison
purposes only, rather than using additional packages to make up the 36 bits.)
W bus lowers
Bits
Pins/Package
Number Pkgs
Pins, Total
Length, mils
Width, mils
Area/Pkg, Sq Mils
Total Area
Relative Area
Bits
Pins/Package
Number Pkgs
Pins, Total
Length, mils
Width, Total
Area, Sq Mils
Total Area
Relative Area
32
20
4
80
23!
80,370
321,480
1.00
36
24
4
96
342
235
80,370
321,480
1.00
32
20
4
80
500
406
812,000
2.53
32
48
2
96
600
406
243,600
487,200
1.52
>4
4
96
600
406
243,600
974,400
3.03
36
24
4
96
600
406
243,600
985,768
1.52
32
84
1
84
780
780
608,400
608,400
1.89
36
64
160
1
160
1255
1255
1,575,025
1,575,025
2.45
72
100 200
1
100
880
880
774,400
774,400
2.41
1
200
1252
1252
1 ,567,504
1,567,504
2.44
QUALITY SEMICONDUCTOR INC.
AN-08: QSOP Packages for 32-bit Buses
The QSOP requires the least area of the four. The next smallest package, the Tl Widebus™, requires
1 .52 times as much board space. What is more interesting is that the equivalent gate array solution in the
smallest practical Quad Flat Pack (QFP) package requires 1 .89 times as much area for 32-bit buses and
2.41 times the area for 36-bit buses. Doubling the bus to 64 or 72 bits makes the situation worse. A 64-bit
or 72-bit gate array in PQFP requires 2.44 times the area of that required by the equivalent 8 QSOPs.
QSOPs Provide Higher Density Than Gate Arrays
A QSOP design uses approximately half the board area of a gate array design.
At first, it may seem surprising that the QSOP provides higher density than an equivalent gate array in a
high density PQFP package. This goes against current conventional wisdom. Gate arrays do provide high
density for logic functions, such as PC chip sets which combine the logic for several packages into one
gate array. This eliminates pins, packages and board area.
When two buses must be connected, however, the pins cannot be eliminated. Two 32-bit buses require
64 pins to connect them, plus power, ground and control signals. This adds up to approximately 80 pins.
The question then becomes how to most efficiently put these 80 pins on a board. The QSOP collects
these pins in four groups of 20 with each group of 20 in two closely spaced rows of 1 0 pins on 25 mil
centers. The PQFP places these 80 pins around the perimeter of a square. The problem is that the area
of this square goes up as the square of the number of pins. Doubling the number of pins increases the
board area by a factor of four, not two. This is why the increasing the size of the PQFP makes the problem
worse, not better.
An additional advantage of the QSOP approach is that the parts are already designed. Not only
designed, but available. Over 70 FCT parts are immediately available in the QSOP package, including the
fastest speed C and D grades and the FCT2000, 25Q output series for high speed with low noise.
FCT In QSOP Solves Board Area. Trace Delay and Noise Problems
The designer of high speed 32-bit RISC or CISC systems has a problem. Address drivers and data
transceivers are required to drive RAM and I/O buses. These transceivers require significant board area,
even when packaged in SOIC. Using a gate array does not solve the problem; it makes it worse. In
addition, the board area required by these parts increases trace length on the PC board causing trace
delay and ringing. At 150-200 picoseconds per inch, it does not take very many inches of trace to add
significant delay to a 33 to 50 mHz design. By minimizing the board area required for bus control, the
QSOP can make the overall design smaller, faster, and lower in noise.
Because the QSOP package is small, it provides logic parts such as the FCT family with higher speed and
lower ground bounce due to its lower lead inductance. Also, the FCT2000 series with 25£2 outputs is also
available in the QSOP package for noise critical high speed applications. The internal 25Q resistors in the
FCT2000 parts save board space. In fact, adding an external SOIC resistor pack would require almost
three times as much additional area as the QSOP itself!
QSOP - The Choice for High Density Designs
QSOP packages significant provide reduction in board space, trace delay and noise for high speed RISC
and CISC designs as well as for high density designs such as laptop and notebook PC's. Because of its
clear advantages and the availability of a full family of parts in the package, the QSOP will become the
package of choice for advanced designs in the 90's.
QUALITY SEMICONDUCTOR INC.
AN-09 : CMOS Bus Switches Provide Zero Delay
=
Q
CMOS Bus Switches
Provide Zero Delay
Bus Communication
by
David Wyland
Application
Note
AN-09
The 74QST3383 and 74QST3384 CMOS Bus Switches by Quality Semiconductor are high speed TTL
bus connect devices. When they are enabled, the bus switches directly connect two buses with a
connection resistance of less than 5Q. They are like a 5 nanosecond multi-pole relay for TTL signals with
an on resistance of 5Q. Since these devices directly connect the bus signals they introduce no additional
propagation delay, timing skew or noise. They are also inherently bidirectional and dissipate no additional
power. They can replace traditional TTL buffers and transceivers to reduce propagation delay, noise,
control complexity and power dissipation.
A block diagram of the 74QST3384 CMOS Bus Switch is shown in Figure 1 . This device consists of ten
switches arranged as two banks of five. This allows the 3384 to be used as a 1 0-bit switch or as a 5-bit, 2-
to-1 multiplexer. A block diagram of the 74QST3383 CMOS Bus Exchange Switch is shown in Figure 2.
This device consists of two banks of ten switches arranged to gate through or exchange two banks of five
signals. This allows the 3384 to be used as a 1 0-bit switch or as a 5-bit, two way bus exchange device.
This part is particularly useful for exchange and routing operations such as byte swap, crossbar matrices,
and RAM sharing.
PIN DESCR
IPTION
Name
I/O
Function
AO-9
I/O
Bus A
BO-9
I/O
Bus B
BEA7BEB
I
Bus Switch Enable
1 UI1VI
BEA"
BEB
BO-4
B5-9
Function
H
H
Hi-Z
Hi-Z
Disconnect
L
H
AO-4
Hi-Z
Connect
H
L
Hi-Z
A5-9
Connect
L
L
AO-4
A5-9
Connect
Figure 1: 74QST3384 CMOS Bus Switch Block Diagram
Each switch consists of an N channel MOS transistor driven by a CMOS gate. When the switch in enabled,
the gate of the N channel transistor is at Vcc (+5 volts) and the device is on. These devices have an on
resistance of less than 5Q for voltages near ground and will drive in excess of 64 mA each. The resistance
rises somewhat as the I/O voltage rises from a TTL low of 0.0 volts to a TTL high of 2.4 volts. In this region
the A and B pins are solidly connected, and the bus switch is specified in the same manner as a TTL
device over this range. As the I/O voltage rises to approximately 4.0 volts, the transistor turns off. This
corresponds to a typical TTL high of 3.5 to 4.0 volts.
-
QUALITY SEMICONDUCTOR INC.
AN-09 : CMOS Bus Switches Provide Zero Delay
PIN DESCR
IPTION
Name
I/O
Function
AO-4, BO-4
I/O
Buses A, B
CO-4, DO-4
I/O
Buses C, D
BE
BX
1
Bus Exchange
BE
BX
AO-4
BO-4
Function
H
X
Hi-Z
Hi-Z
Disconnect
L
L
CO-4
DO-4
Connect
L
H
DO-4
CO-4
Exchange
Figure 2: 74QST3383 CMOS Bus Exchange Switch Block Diagram
The bus switch provides a low resistance connection between inputs and outputs for voltages below 3.0
volts. As the I/O voltage rises above 3 volts, the resistance increases until the switch turns off, at
approximately 4.0 volts. This is shown in Chart 1 , a Vin versus Vout chart. The switch on resistance is
determined by the lower of the voltages on the two I/O pins. The resistance rises as the I/O voltage rises,
as shown in Chart 2.
Vout vs Vin for Various Loads, Typical
Vout
5.0
4.0
3.0
2.0
1 .0
>.♦.♦ • • <
I
"TV"'
I
—
•■-1 KQ
■D-10KQ
— 10 Megn
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vin, Volts
Chart 1: Vout vs Vin
6-66
QUALITY SEMICONDUCTOR INC.
■
AN-09 : CMOS Bus Switches Provide Zero Delay
On Resistance vs Vin @ 4.75 Vcc
Ron, £l
1 6
1 4
1 2
1 0
8
6
4
2
0
0.0
0.5
1 .0
1.5 2.0
Vln, Vo
2.5
3.0
3.5
Chart 2: Switch On Resistance vs Vln
The bus switch provides a path for a driving device to drive capacitance to ground and to drive capacitance
up from ground. This is shown in Figure 3. When the A (or B) input is driven to a TTL low of 0.0 volts, the
N channel transistor is fully on and the B (or A) output will follow it. Likewise, when the A (or B) input is
driven from a TTL low of 0.0 volts to a TTL high, the capacitor side of the N channel switch is at 0.0 volts,
the switch is fully on and the B (or A) output will follow it through threshold and beyond. This means that
the rise and fall time characteristics and waveforms of the B (or A) output will be determined by the TTL
driver, not the bus switch. The switch introduces no propagation delay, to a first approximation.
TTL High to Low Transition
+3.5 => 0V
50
TTL Low to High Transition
0 => 3.5V
5Q
TTL Driver
74FCT244C, etc.
T
+5
Load
Capacitance
TTL Driver
74FCT244C,
I
+5 Load
Capacitance
Figure 3: CMOS Bus Switch Operation
When the bus switch is disabled, the N channel transistor gate is at 0.0 volts, and the transistor is off. By
the nature of the N Channel transistor design, the A and B pins are fully isolated when the transistor is off.
Leakage and capacitance is to the chip substrate (i.e., ground) rather than between input and output.
This minimizes feedthrough in the off state. Because only an N channel transistor is used, either A or B
pin(s) can be taken to Vcc and above, and the device can be powered down without loading either bus.
The bus switch can replace drivers and transceivers in systems if bus repowering is not required. Since
the bus switch directly connects two buses, it provides no drive of its own but relies on the device that is
driving data onto the connected buses. If the additional loading of the connected bus is small enough,
there is a net gain in speed. For example, the sensitivity to loading of a driver such as the 74FCT244 is
typically 2 ns/1 00 pF. If the connected bus adds 50 pF of loading the added delay will be 1 ns. This is
much less than the 4 to 1 0 ns delay of the buffer or transceiver the bus switch replaces.
QUALITY SEMICONDUCTOR INC.
6-67
Microprocessor Shared Memory Connect tpr Slave Processor
Figure 4 shows the 3384 bus switch used to allow the memory for a DSP slave processor to be accessed
by the host processor. A 33 mHz TMS320C30 system is shown with a 1 6Kx32 SRAM as its program and
data storage memory. The SRAM is connected to the DSP CPU by a 3384, allowing full speed operation
while the CPU is running. This saves 10 ns over using conventional fast buffers and transceivers, i.e. 5
ns for a 244 address buffer to the SRAM and 5 ns for an 245 address transceiver from the SRAM, as
shown in the timing diagrams. This allows using SRAMs with 35 ns Taa instead of 25 ns. Between
calculations, the 3384's disconnect the SRAM from the DSP CPU and connect it to the host CPU,
allowing the host to write data in before the DSP calculation and read data out after.
TMS320C30
DSP CPU
33 mHz
3384
Data
3384
3384
Host CPU
System
Host System Bus
Address
3384
R/W, OE
I
16KX32
SRAM
25 ns
3384
Timing with 3384
320030 H1 ciockT
DSP Address Out
3384 Address Sw Out
SRAM Taa
3384 Data Sw In
irf^k ; Valid Address ; ^
With 244/245
DSP Address Out
244 Address Bfr Out
SRAM Taa
3384 Data Sw In
Valid Address
( 35_n&_Iaa ^Qata SeUip
Valid Data
Valid Address
Valid Address
3
( 25 ns Taj~^j Data Setijp
Qj< Valid Data S
Figure 4: 74QST3384 as DSP Shared Memory Connect
QUALITY SEMICONDUCTOR INC.
AN-09 : CMOS Bus Switches Provide Zero Delay
Multiprocessor System Fast Bus Connect
Figure 5 shows the 3384 bus switch used as a fast bus connect in a high performance multiprocessor
system. Four 32-bit processors are shown, each with its own cache or other local memory. Each
processor is connected by a 3384 bus switch to a 1 meg x 32, 25 ns cycle time fast SRAM main memory.
The 3384 is used to connect the address, data, and control lines of the SRAM directly to each processor.
When one of the 3384's is active, the main memory appears as a simple SRAM to the connected CPU.
This provides a simple, very fast interface with no additional delays for buffers or data direction logic and no
timing skew in the control signals.
32-bit
32-bit
32-bit
32-bit
CPU
CPU
CPU
CPU
3384
i i
1 t
Cache
[
3384
3384
Cache
&
3384
Cache
3384
I
Cache
3384
3384
3384
^~ ^ ^ ^
Main Memory
1 meg x 32
25 ns
Fast SRAM
Figure 5: 7.
4QST3384
as Multiprocessor System Bus Connect
6-69
AN-09 : CMOS Bus Switches Provide Zero Delay
Bgs Exchange Switch fpr Ping Ppng Memory Connect
Figure 6 shows the 3383 bus exchange switch used to connect two memories to a DSP processor and a
host CPU bus. The 3383 connects Memory A to either the DSP or host CPU, and Memory B to the host
CPU or DSP CPU, respectively, depending on the state of the bus exchange control. This configuration
allows the host CPU to be accessing one memory for loading program and data or retrieving results while
the DSP CPU is running out of the other memory. When the calculation is complete, the memories are
exchanged, and the DSP CPU can continue with another calculation while the results of the last one are
accessed. This configuration allows both high speed and high throughput.
Memory A
TMS320C30
DSP CPU
33mHz
Host CPU
System
Figure 6: 74QST3383 for Ping Pong Memory Connect
The Ping Pong memory configuration can also be used to pipeline results between processors, as shown
in Figure 7. All processors transfer data from their input memories to their output memories. When one
pass is complete, the memories are exchanged and the output of one processor becomes the input of
the next.
Fast
Fast
Fast
Fast
RAM
RAM
RAM
RAM
rr tj
| 3383 Bus Ex~| I 3383 Bus Ex I I 338
.JITIJ
3383 Bus Ex
Data Out
DSP
DSP
CPU
CPU
Figure 7: 74QST3383 for Ping Pong Pipeline Memory
6-70
QUALITY SEMICONDUCTOR INC.
AN-09 : CMOS Bus Switches Provide Zero Delay
Bus Exchange Switch tor Crossbar Systems
Figure 8 shows the 3383 bus exchange switch used to connect four CPUs and four memories in a
crossbar configuration. In this configuration, any CPU can be connected to any memory. If there is no
conflict by two CPUs for the same memory, any valid combinations of CPU and memory can be made by
appropriate selection of the 3383 controls. Two layers of 3383 bus exchange switches are required for
this four-way crossbar. Three layers will be required for an 8-way crossbar, etc.
The 3383 bus exchange switch is ideal for crossbar work because it introduces no delay of its own. A 1 6-
way crossbar with four layers of switches adds little or no delay over direct connection of the RAM to the
CPU. Also, the CPU sees a simple RAM interface without the complicated timing skew requirements
which might be imposed by using bus transceivers instead of 3383 switches.
CPU
< — ►
3383
3383
4 — ►
RAM
CPU
3383
«* — ►
**• /
A
/ \
CPU
RAM
CPU < » * +-\ /-» t ^ ► RAM
3383 / \ 3383
CPU ► Wr- 5* ► RAM
3383
< ►
RAM
\ J
\ /
RAM
Figure 8: 74QST3383 Crossbar Switch
Bus Exchange Switch for Bus Bvte Swap and Barrel Shift
A scheme similar to the one shown in the diagram of Figure 8 can also be used to provide byte swap
capability between a CPU and memory. This is useful in systems where big-endian and little-endian byte
orders are mixed within the same system. If the CPU and RAM blocks of figure 8 are interpreted as bytes
of a CPU and memory bus respectively, the crossbar switch scheme shown allows any combination of byte
swapping or shifting desired without introducing any additional propagation delay or control
considerations. If this concept is extended to the bit level, a barrel shifter results.
AN-09 : CMOS Bus Switches Provide Zero Delay
Fast Address latch
Figure 9 shows the 3384 bus switch used as a fast address latch in an SRAM memory subsystem. In this
system, the 3384 connects the SRAM to the address bus, which drives the stray capacitance of the
SRAM array. When the 3384 turns off, the stray capacitance holds the TTL level. The advantage of using
the 3384 instead of a fast latch such as the 74FCT373 is that the effective throughput delay is much less.
The delay caused by the additional 50 pF load on the address bus may be 1 ns as compared to 4 ns for the
fastest latch. Also, the 3384 does not introduce additional noise.
■
The hold time for typical capacitances and leakages can be quite long compared to the clock cycle times of
fast systems. For the 1 6Kx32 configuration of eight 1 6Kx4 SRAMs shown, the stray capacitance is of the
order of 50 pF. The turn off transient of the 3384 will typically be less than 50 millivolts. Assuming a 1 volt
change in level and a typical total leakage at operating temperature of less than 50 nanoamperes, (SRAMs
+ 3384), the hold time is of the order of (50 x 1 0E-1 2/50 x 1 0E-9) = 1 millisecond. If an indefinite hold is
desired, an active terminator can be added as shown in the drawing.
Address Bus
CPU
1 6Kx32
10 ns SRAM
8 x 8886
Active Terminator
Data Bus
Figure 9: 74QST3384 Fast Address Latch
i
— — -
6-72
QUALITY SEMICONDUCTOR INC.
AN-09 : CMOS Bus Switches Provide Zero Delay
ATE Load Switch
Figure 1 0 shows the 3384 bus switch used as a load switch for an automated test equipment (ATE) load
board. ATE equipment requires custom design of the load board (i.e. electrical test fixture) for a given
device to be tested. A common problem to be solved is the connection and disconnection of load resistor
network to each pin of the device under test (DUT). The load must be connected during parts of the test
and disconnected during other parts. This connection is typically done with small relays because of their
low on resistance. However, relays are large and slow. The 3384 bus switch can replace up to 10 relays in
this application, in a smaller package, and with an actuation time of 6 nanoseconds rather than 5
milliseconds. This can significantly speed up test time.
3384
Switches Load Circuits
ATE
Drivers
&
Comparators
Device
Under
Test
480Q
J-
Vcc
480£i
480ft
Vcc
Vcc
Figure 10: 74QST3384 ATE Load Switch
Conclusion
The 74QST3383 and 3384 bus switches are new tools for the system designer. They can be used to
reduce propagation delay and to create high speed systems with simplified interfaces, improved timing
margins and reduced noise.
QUALITY SEMICONDUCTOR INC.
6-73
AN-09 : CMOS Bus Switches Provide Zero Delay
6-74
QUALITY SEMICONDUCTOR INC.
.5 'J
General Information 1
Static RAM Products 2
FIFO Memory Products 3
FCT-T Logic Products 4
QuickSwitch Products 5
Application Notes 6
Package Information 8
Sales Offices 9
QUALITY SEMICONDUCTOR INC.
QUALITY
SEMICONDUCTOR INC.
Quality and Reliability Program
■
QUALITY AND RELIABILITY PROGRAM
Quality and Reliability Operation Overview
At Quality Semiconductor Inc., we are committed to maintaining the highest possible standards of quality
and reliability in our products. We do not merely screen for quality - we design our products for quality and
reliability. We consider our quality/reliability goals met when customers are satisfied with our products.
We achieve high standards of quality and product excellence by using better materials, controls and
designs. This translates to building quality into the product from its inception.
We use three quality enhancement techniques: (1) We build product reliability into each design, and
every employee is responsible for ensuring we attain such reliability; (2) We build product quality into all
stages of the manufacturing process through strict inspections of incoming materials and conformance
checks after critical process steps. We monitor all processes to ensure they adhere to specifications; (3)
After burn-in, we perform stringent inspections and reliability conformance checks on products to ensure
they meet final product quality requirements.
Quality and Reliability in the Design Stage
Our development philosophy maintains a team effort among design, layout, technology, package, testing
and product engineers who are involved throughout the product cycle.
The Quality and Reliability organization is ultimately responsible for assuring our products meet
established standards. This group supervises fabrication techniques, assembly processes, packages and
product designs.
At QSI we are expert in fabrication process reliability, assembly/process/package reliability and product
reliability. All development group team members address quality and reliability issues early in the
development cycle. Our goal is to build a product to the highest possible standard and to satisfy our
customers.
Our Technology Development and Production Engineering groups work as a team from the early
development stage to ensure a smooth transition of technology into production. The development
activity begins with the need for a higher speed product at small die sizes, or a reduced die size product or
even a new product. To transfer a process to production requires that the process be capable of meeting
the performance, cost-effectivity and manufacturability targets. To satisfy these goals, the Technology
Development group balances many variables to produce fabrication technology. QSI's Process Reliability
group scales geometries in the quest for higher speed procucts, simultaneously ensuring the technology
is inherently reliable.
QUALITY SEMICONDUCTOR INC.
7-1
Quality and Reliability Program
To guarantee reliable operation throughout the lifetime of the product, the following must be true:
• The technology ensures the absence of any intrinsic wearout mechanisms
• Defect densities are low enough to allow efficient and economical manufacturing
• Circuit design and layout rules have sufficient margins
Our Package Development team satisfies the constant demand for newer packages and assembly
processes. The performance requirements for newer packages and assembly processes are very
complex. As we push performance limits, the electrical parasitics of a package can impact the overall
device specification. The team carefully selects packages to meet the increased speed requirements.
Our Package Reliability and Technology Development teams share a common goal: to produce a reliable,
manufacturable product that meets the customers' need for functionality, performance and cost.
QSI's Production Engineering team ensures the functionality and performance targets have been met.
This team concentrates on all the above-mentioned areas, especially design and test. Extensive test
programs excite every node in the device to ensure excellent fault coverage. The team resolves product
yields and performance issues and handles product failure analysis. Production Engineering provides
feedback to other QSI teams and to customers on any detected failure mechanisms. The team
immediately implements a corrective action procedure to remedy the problem.
■
Product Testing Categories
Quality Semiconductor uses MIL-STD-883 to determine test methods, procedures and specifications.
Thus, our customers purchase commercial devices that receive military patterned process flow at no
additional cost.
At QSI, we offer three distinct testing categories:
1 ) Commercial operating range 0°C to +70°C.
2) Military Grade product processed to MIL-STD-883 and operating from -55°C to +1 25°C.
3) SMD (Standard Military Drawing) approved product; Military operating range; -55°C to +125°C,
electrical tested per the applicable Military drawing.
Flow Charts
The Commercial Test Flow Charts are shown on the following pages. Detailed process flows for plastic
and hermetic packages are discussed.
^BSSBB^BSBBBSSSBBBBBSBBSBSSSS=
7-2 QUALITY SEMICONDUCTOR INC.
Quality and Reliability Program
INCOMING WAFER
100% Saw Through
Die Visual 100% Inspection
Par MIL-STD-883 Method 2010 Condition B
PLASTIC ASSEMBLY FLOW
Sample Inspect die at 0,4% AQL
Inspect Die Placement
Incoming Gold Wire O EPDHY Cure
QA Sample. Functional T
__/\ QA Monitor
Perform Attachement Strength
Q Wire Bond
ial
y L
Incoming Molding Compound
QA Monitor
Perform Bond Strength Per
MIL-STD-S83 Method 2011
QA Monitor
Bond Pad Crater Check
Per QSI Detailed Specification
Internal Visual mat Inspection
Low Power (30X) Inspect for
Workmanship
QA Visual Gale
Sample Inspect to Verify
Workmanship at 0.65% AQL
Die Coal mil Cure
QA Sample. Functional
J p^'u1' ,ApP'ied 10 SeleC'ed
External Visual at O.S5% AQL
Pre-Burn-ln Electrical Test at +25-C
V Within Limits
Top Mark/Cure
Final Visual Inspection
Sample External Visual at 0.65% AQL
Sample Electrical Test at 0.1% AQL
J Quality Assurance Lot Acceptance
o
-
-
^^^^=^= ^^^^^=== ^^^^^^=
QUALITY SEMICONDUCTOR INC. 7-3
Quality and Reliability Program
Plastic Package Process Flow Summary
Refer to the Plastic Package Processing Flow diagram. All test methods refer to MIL-STD-883 unless
stated otherwise.
1 .0 Wafer Fabrication
Humidity, temperature, and particulate contamination levels are controlled and maintained according to
criteria patterned after Federal Standard 209, Clean Room and Workstation Requirements. All critical
workstations are maintained at Class 1 0 levels or better.
All wafers lots are sample inspected for die visual rejects and checked for wafer thickness.
3,0 Wafer Mounty saw/ Clean
Wafers are mounted on sticky tape and then 100% cut through at 12 Megohms minimum D.I. water
resistivity. The cut wafers are subjected to high D.I. water pressure cleaning then dried with infrared lamp.
4.0 Die Visual 100% inspection
The individual die are 100% visually inspected under high power scope per MIL-STD-883 Method 2010
Condition B.
5-Q Die Attach
The die that are inspected as good are attached to spot silver plated lead frames using silver filled epoxy at
room temperature.
6.0 Epoxy cure
The die attach lead frame are baked at 175°±5°C for a minimum of one hour under nitrogen or dry air
environment to ensure die attach integrity. The attachment strength is routinely measured per MIL-STD-
883 Method 2019.
■
7.0 Wire bond
The bond pads are connected to lead frame fingers by thermosonic ball bond method employing 1 .3 mils
diameter gold wire. The wire bond strength is routinely measured as per MIL-STD-883 Method 2011.
Additional checks on bond pad crater are carried out on bonded products to insure integrity of the wire
bond process.
8,Q Internal Visual 10Q% Inspection
The bonded products are 100% visually inspected to ensure good workmanship prior to encapsulation.
9,0 Die Coat and Cure
Silicon Gel Coating is applied to selected products for the following purposes:
To act as a barrier for alpha-particle protection
To reduce stress on die surface
To provide additional moisture resistant barrier
1Q.Q Moid/Encapsulate
7-4 QUALITY SEMICONDUCTOR INC.
Quality and Reliability Program
==================================
The bonded products are molded to protect the dice and wires using low stress molding compound at
175°±5°C. X-ray, on the molded products, is routinely carried out to address wires sweep and internal
package void
11.0 Back Mark
All products are marked on the back to maintain lot traceability and assembly location traceability.
12.0 Post Mold Cure
Molded and marked products are baked at 175°±5°C for a minimum of six hours to ensure optimum plastic
sealing.
13,0 Chemical Deflash
Products are subjected to heated M-pyrol to remove plastic bleed and flash on leads outside the package
body. This step is necessary to ensure good lead finish coverage.
14.0 Dejunk/Trim/Form/ Derail
These steps remove mechanical flash between leads, cut off dambar from external leads, form the leads to
specific shapes and singulate products into individual units. Packages outline are routinely measured to
ensure that singulated units meet specified dimensions.
15.0 Lead Finish
All product leads are protected for corrosion by solder dip for through-hole packages and by solder plate
for surface mount packages. Solder thickness measurements and solderability tests are routinely carried
out to ensure the integrity of the soldering process.
16.0 External Visual 100% inspection
The finished products are 100% inspected for external mechanical and lead finish quality. All inspected
lots are sampled per AQL method for lot acceptance.
17.Q Pre-burn-in Electrical Test
Every product is 1 00% electrically tested at +25°C to QSI data sheet specification or customer given
specification.
18.0 Burn-In/ Dynamic
All plastic package products are burned-in at +125°C for a minimum of 16 hours.
19.0 Post Burn-In Electrical Test
All plastic package products are electrically tested to QSI data sheets or customer given specifications at
+70°C minimum. The Percent Defective Allowable (PDA) is 5% maximum. All tested lots are 100%
verified to ensure PDA is within limits.
20,0 Top Mark
All products are top marked with product type and date code
21 ,o Final Visual Inspection
===== 1 =
QUALITY SEMICONDUCTOR INC. 7-5
Quality and Reliability Program
Each product is 100% inspected for conformance to package specification.
22.Q QA Lot Acceptance
All final products are visually sampled and also electrically tested on a sample basis to comply with all AQLs.
-
1
7-6 QUALITY SEMICONDUCTOR INC.
Quality and Reliability Program
Incoming Package
OA Sample
Visual/ Dimension/
Functional
INCOMING WAFER
HERMETIC ASSEMBLY FLOW
QA Monitor
Bum LmK Teal
Per MIL-STD-883 Method 1014
■
Hermetic Package Process Flow Summary
a
QUALITY SEMICONDUCTOR INC.
7-7
Quality and Reliability Program
Refer to the Hermetic Package Processing Flow diagram. All test methods refer to MIL-STD-883 unless
stated otherwise.
1.0 Wafer Fabrication
Humidity, temperature, and particulate contamination levels are controlled and maintained according to
criteria patterned after Federal Standard 209, Clean Room and Workstation Requirements. All critical
workstations are maintained at Class 1 0 levels or better.
•
2.0 Wafer incoming
All wafers lots are sample inspected for die visual rejects and checked for wafer thickness.
3,0 Wafer Mount/ Saw/ Clean
Wafers are mounted on sticky tape and then 1 00% cut through at 1 2 Mega-ohms min D.I. water resistivity.
The cut wafers are subjected to high D.I. water pressure cleaning then dried with infra-red lamp.
4.0 Die Visual 1 00% inspection
The individual die are 100% visually inspected under high power scope per MIL-STD-883 Method 2010
Condition B.
5.0 Die Attach
The good dice are attached to ceramic package using gold/silicon eutectic method. The attachment
strength is routinely measured per MIL-STD-883 Method 2019.
6,0 Wire Bond
The bond pads are connected to package fingers by ultrasonic wedge bond method employing 1 .25 mils
diameter aluminum wire. The wire bond strength is routinely measured as per MIL-STD-883 Method
201 1 . Additional checks on bond pad crater are carried out on bonded products to insure integrity of the
wire bond process.
7,0 Internal Visual 1QQ% Inspection
All bonded products are 100% visually inspected per MIL-STD-883 Method 2010 condition B.
8.0 Die Coat and Cure
Die Coating is applied to selected products for alpha-particle protection.
9,0 Seal
The bonded products are sealed to protect the dice and wires. Visual, lid-torque and hermeticity are
routinely checked for high quality standard.
1Q.Q Back Mark
All products are marked on the back to maintain lot traceability and assembly location traceability.
11, Q Environmental Conditioning
All sealed products are subjected to thermal and mechanical stress tests. This is to eliminate products with
marginal die attach, wire bond or seal integrity.
7-8 QUALITY SEMICONDUCTOR INC.
Quality and Reliability Program
12.0 Hermetic Testing
■
All stress tested products are subjected to fine and gross leak tests to eliminate marginally sealed
products or products whose seals may have become defective as a result of environmental conditioning
tests.
13.0 External Visual 100% inspection
The finished products are 1 00% inspected for external mechanical and lead finish quality. All inspected
lots are sampled per AQL method for lot acceptance.
14.0 Pre-burn-in Electrical Test
Every product is 1 00% electrically tested at +25°C to QSI data sheet specification or customer given
specification.
15,0 Burn-In/ Dynamic
All hermetic package products are burned-in per QSI applicable device specification.
Post Bum-In Electrical Test
All hermetic package products are electrically tested per QSI applicable device specification. The Percent
Defective Allowable (PDA) is 5% maximum. All tested lots are 100% verified to ensure PDA is within limits.
17.0 Tod Mark
All products are top marked with product type and date code
18.0 Final Visual Inspection
Each product is 100% inspected for conformance to package specification.
19.0 QA Lot Acceptance
All final products are visually sampled and also electrically tested on a sample basis to comply with all AQLs.
QUALITY SEMICONDUCTOR INC.
Quality and Reliability Program
Reliability Monitor Program
The Reliability Monitor Program is Quality Semiconductor procedure described under Quality
Specification QARP-00001-00, which is available to customers upon request. This specification
describes a procedure that provides for periodic reliability monitors to ensure all Quality Semiconductor
products comply with established goals for improving reliability and minimizing reliability risks to our
customers. The Reliability Monitor program is based on monitoring key products within each generic
process family. This procedure requires that detailed failure analysis be performed on all test rejects and
corrective action be taken as indicated by the analysis. A summary of the Reliability Monitor Program test
and sampling plan is shown below.
Reliability Monitor Program Sampling Plan
Test
Conditions
LTPD
Sample Size /
Acceptance
Frequency
Plastic
Hermetic
Infant
Mortality
160 Hours @ 125 X/5.5V
Dynamic burn-in
3
129/1
129/1
Monthly
■
Operating
Life
1000 Hours @ 125 "C/5.5V
Dynamic burn-in
5
105/2
105/2
Quarterly
Thermal
Shock
100 Cycles: -65 °C to 150 °C,
MIL-STD-883, Method 1011
5
105/2
105/2
Monthly
Temperature
Cycle
100 Cycles: -65 °C to 150 °C,
MIL-STD-883, Method 1010
5
105/2
105/2
Quarterly
Pressure
Cooker
1 60 Hours @ 121 °C
15PSI, Unbiased
3
129/1
NA
Monthly
85/85
Moisture,
Biased
1 000 Hours @ 85 °C,
85% Relative Humidity,
Biased
5
105/2
NA
Quarterly
7-10
QUALITY SEMICONDUCTOR INC.
General Information
Static RAM Products
FIFO Memory Products
FCT-T Logic Products
QuickSwitch Products
Application Notes
6
Quality And Reliability
Package Informati
Sales Offices
9
QUALITY SEMICONDUCTOR INC.
QUALITY SEMICONDUCTOR INC.
Package Information
PACKAGE INFORMATION
QSI uses a two character package code in the part numbers of its products to indicate the package. The
package code is uniform over all part numbers unless otherwise noted. The following is a table of these
package codes and their corresponding package. The package outline drawings for each of these
packages is shown on the following pages.
QSI Package Codes
PkflCode PactooeType
Comments
D
D4
D6
J
JR
Ceramic DIP, 300 mil
Ceramic DIP, 400 mil
Ceramic DIP, 600 mil
Plastic PLCC, square
Plastic PLCC, rectangular
L
LR
P
P4
P6
PDIP, 300 mil
PDIP, 400 mil
PDIP, 600 mil
QSOP, 150 mil gull wing 25-mil pitch
SO
S1
S2
S3
S5
SOIC, 300 mil gull wing
SOIC, 150 mil gull wing
SOIC, 200 mil gull wing
SOIC, 330 mil gull wing
SOIC, 350 mil gull wing
V
V3
V5
SOJ, 300 mil J-bend
SOJ, 330 mil J-bend
SOJ, 350 mil J-bend
ZIP, zig-zag in-line
=
QUALITY SEMICONDUCTOR INC.
Ceramic Dual In-Line
Packages14-28 Pin (300 mil)
Pln1
nnnnn
n n n
E E1
IE
uuuu
(
uuuu
N
►
-► B1 ^
e|^- ^ SEATING PLANE ^ eA ►
Notes : 1 . Refer to applicable symbol Iist2. N is the maximum
quantity of lead positions3.AII dimensions are in inches4.
Dimensions D and E1 are to be measured at ma
material condition.
JEDEC#
MO-036AC
MO-036AD
N/A
N/A
MO-058AA
MO-058AB
DWG#
CD14A
CD16A
CD20A
CT22A
CT24A
CT28A
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
.135
.175
.135
.175
.160
.200
.160
.200
.160
.200
.160
.200
A1
.025
.040
.025
.040
.015
.040
.015
.040
.015
.040
.015
.040
B
.016
.020
.016
.020
.016
.020
.016
.020
.016
.020
.016
.020
B1
.045
.060
.045
.060
.045
.070
.045
.070
.045
.070
.045
.060
C
.009
.012
.009
.012
.009
.012
.009
.012
.009
.012
.009
.012
D
.770
.810
.770
.810
.950
.990
1.060
1.100
1.240
1.280
1.440
1.480
E
.300
.325
.300
.325
.300
.325
.300
.325
.300
.325
.300
.325
E1
.240
.290
.240
.290
.260
.310
.260
.310
.260
.310
.260
.310
e
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
8A
.310
.380
.310
.380
.310
.380
.310
.380
.310
.380
.310
.380
L
.125
.150
.125
.150
.125
.150
.125
.150
.125
.150
.125
.150
S
.070
.090
.025
.045
.025
.045
.030
.050
.070
.090
.070
.090
N
14
16
20
22
24
28
QUALITY SEMICONDUCTOR INC.
=
Package Information
PLCC
Plastic Leaded Chip Carrier (PLCC)
D
JUUUUUU
Notes :
1 . Refer to applicable symbol list
2. All dimensions are in inches
3. Dimensions D1 and E1 are to be measured at maximum material condition
but do not include mold flash. Allowable mold flash is 0.010 inch per side
4. Lead coplanarity is 0.004 inch maximum.
JEDEC #
MO-052 AE
MO-047AD
DWG#
PL32A
PL52A
Symbol
Min
Max
Min
Max
A
.115
.135
.165
.180
A1
.070
.090
.090
.120
A2
.015
.035
.015
.035
B
.026
.032
.026
.032
B1
.014
.019
.014
.019
C
.009
.012
.009
.012
D
.485
.495
.785
.795
D1
.448
.452
.750
.756
D2
.390
.430
.690
.730
D3
.300 REF
.600 REF
JEDEC #
MO-052 AE
MO-047 AD
DWG#
PL32A
PL52A
Symbol
Min
Max
Min
Max
E
.585
.595
.785
.795
E1
.548
.552
.750
.756
E2
.490
.530
.690
.730
E3
.400 REF
.600 REF
e
.044
.056
.044
.056
h
.042
.048
.042
.048
ND
7
13
NE
9
13
8-3
Package Information
Chip
(LCC)
■
D —
*
*- JX45
Notes :
1 . Refer to applicable symbol list
2. All dimensions are in inches
3. ND » NE - number of leads per side
A1
■1
JEDEC #
N/A
MO-027AA
DWG#
CL20A
CL28A
Symbol
Min
Max
Min
Max
A
.064
.090
.064
.090
A1
.054
.066
.054
.066
B1
.022
.028
.022
.028
B2
.022
.041
.022
.041
D
.342
.358
.442
.458
D1
.075 REF
.075 REF
D2
.200 BSC
.300 BSC
D4
.358
.458
D5
.250 REF
.350 REF
E
.342
.358
.442 | .458
E1
.075 REF
E2
.200 BSC
.300 BSC
E4
.358
.458
E5
.250 REF
.350 REF
e
.050 BSC
.050 BSC
h
.040 REF
.040 REF
i
.020 REF
.020 REF
L
.045
.055
.045
.055
L2
.077
.093
.077
.093
N
20
28
ND
5
7
Package Information
300 Mil PDIP
<4
Plastic Dual In-Llne Packages
14-28 Pin (300 mil)
~n n n
E E1
is
Pin 1
nnnnn
u u u u
D
UTJTJTJ
N
fc>
1
L
T
"J SEATING PLANE
Notes:
1 . Refer to applicable symbol list
2. N is the maximum quantity of lead positions
3. AII dimensions are in inches
4. Dimensions D and E1 are to be measured at maximum
material condition but do not include mold flash.
JEDEC #
MS-001 AC
MS-001 AA
MS-001 AE
N/A
MS-001 AF
MO-095 AH
DWG#
PD 14A
PD 16A
PD 20A
PT22B
PT24A
PT28A
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
.130
.170
.130
.170
.130
.170
.130
.170
.130
.170
.130
.180
A1
.015
.040
.015
.040
.015
.040
.015
.040
.015
.040
.015
.040
B
.016
.020
.016
.020
.016
.020
.016
.020
.016
.020
.016
.020
B1
.045
.070
.045
.070
.045
.070
.045
.070
.045
.070
.045
.060
C
.009
.012
.009
.012
.009
.012
.009
.012
.009
.012
.009
.012
D
.745
.765
.745
.765
1.020
1.040
1.020
1.040
1.150
1.260
1.345
1.385
E
.300
.325
.300
.325
.300
.325
.300
.325
.300
.325
.300
.325
E1
.240
.270
.240
.270
.240
.270
.240
.270
.250
.280
.275
.295
e
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
8A
.310
.380
.310
.380
.310
.380
.310
.380
.310
.380
.310
.380
L
.120
.140
.120
.140
.120
.140
.120
.140
.120
.140
.120
.140
S
.070
.080
.020
.035
.060
.070
.010
.020
.025
.080
.020
.040
N
14
16
20
22
24
28
QUALITY SEMICONDUCTOR INC.
8-5
Package Information
600 Mil PDIP
Plastic Dual In-Llne Packages
28-40 Pin (600 mil)
ti n n
E E1
i — JZLU u u u
rru
Pin 1
nnnnn
ETTJTJTJ
N
►
► Sk" -► |-^- B1 |
e ■ f"| SEATING PLANE
Notes:
1. Refer to applicable symbol list
2. N is the maximum quantity of lead positions
3. AII dimensions are in inches
4. Dimensions D and E1 are to be measured at maximum
material condition but do not include mold flash.
Allowable mold flash is 0.010 inch per side.
JEDEC #
DWG#
Symbol
A1
B1
E1
MS-01 1 AB
PD 28A
Min Max
.150
.015
.016
.045
.009
1.440
.600
.530
.090
.610
.120
.070 .090
28
.190
.040
.020
.070
.012
1.460
.625
.560
.110
.680
.140
MS-01 1 AC
PD40A
Min
.150
.015
.016
.045
.009
2.050
.600
.530
.090
.610
.120
.070
Max
.190
.040
.020
.070
.012
2.070
.625
.560
.110
.680
.140
.090
40
QUALITY SEMICONDUCTOR INC.
Package Information
150 MIL QSOP
Quarter Size Outline Package (QSOP) Plastic Small Outline
s Gull Wing 20, 24 Pin (1 50 mil)
T
H E
yyyy mws
i-i
JEDEC #
TBD
TBD
DWG#
PSS-20A
PSS-24A
Symbol
Min
Norn
Max
Min
Norn
Max
A
0.060
0.064
0.068
0.060
0.064
0.068
A1
0.004
0.006
0.008
0.004
0.006
0.008
B
0.009
0.010
0.012
0.009
0.010
0.012
C
0.007S
0.008
0.098
0.0075
0.008
0.098
D
0.337
0.342
0.346
0.337
0.342
0.346
Notes :
1 . Refer to applicable symbol list.
E
0.150
0.155
0.157
0.150
0.155
0.157
2. N is the maximum quantity of
lead positions.
3. All dimensions are in inches.
e
0.025 BSC
0.025 BSC
H
0.230
0.236
0.244
0.230
0.236
0.244
4. Dimensions D and E are to be
measured at maximum material
h
0.010
0.013
0.016
0.010
0.013
0.016
condition but do not include mold
flash. Allowable mold flash is
L
0.016
0.025
0.035
0.016
0.025
0.035
0.006 inch per side.
N
20
24
5. Lead coplanarity is 0.004 inch max.
a
0°
5°
8°
0°
5°
8°
S
0.056
0.058
0.060
0.031
0.033
0.035
s
Package Information
150 Mil SOIC
Plastic Small Outline Gull Wing 14, 16 Pin (SOIC)
(150 mil)
Pln1
f-^HRR RRRRR
H E
uuuu yyyy
Notes :
1 . Refer to applicable symbol list.
2. N is the maximum quantity of lead positions.
3. All dimensions are in inches.
4. Dimensions D and E are to be measured at maximum material condition
but do not include mold flash. Allowable mold flash is 0.006 inch per side.
5. Lead coplanarity is 0.004 inch maximum
A1
JEDEC #
DWG#
Symbol
B
MS-012AB
PS-14B
Min
0.060
0.004
0.014
0.0075
0.337
0.150
Norn
0.064
0.006
0.016
0.008
0.342
0.155 0.157
Max
0.068
0.008
0.019
0.098
0.346
0.050 BSC
0.230
0.010
0.016
0°
0.236
0.013
0.244
0.016
0.025 0.035
14
MS-013AC
PS-16B
Min
0.060
0.004
0.014
0.0075
0.386
0.150
Norn
0.064
0.006
0.016
0.008
0.391
0.155 0.157
Max
0.068
0.008
0.019
0.098
0.393
0.050 BSC
0.230
0.010
0.016
0°
0.236
0.013
0.025 0.035
16
0.244
0.016
5°
8-8
QUALITY
>R INC.
Package Information
300 Mil SOIC
Plastic Small Outline Gull Wing (SOIC)
16-28 Pin (300 mil)
Pin 1
RRR RRRRR
H E
-hx45°
\
Notes :
1 . Refer to applicable symbol list.
2. N is the maximum quantity of lead positions.
3. All dimensions are in inches.
4. Dimensions D and E are to be measured at maximum material condition
but do not include mold flash. Allowable mold flash is 0.006 inch per side.
JEDEC #
MS-013 AA
MS-013 AC
MS-013 AD
MS-013 AE
DWG#
PS16A
PS20A
PS24A
PS 28A
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
A
.096
.104
.096
.104
.096
.104
.096
.104
A1
.005
.011
.005
.011
.005
.011
.005
.011
B
.014
.019
.014
.019
.014
.019
.014
.019
C
.009
.012
.009
.012
.009
.012
.009
.012
D
.402
.412
.500
.510
.602
.612
.701
.711
E
.292
.299
.292
.299
.292
.299
.292
.299
e
.044
.056
.044
.056
.044
.056
.044
.056
H
.396
.416
.396
.416
.396
.416
.396
.416
h
.010
.016
.010
.016
.010
.016
.010
.016
L
.020
.040
.020
.040
.020
.040
.020
.040
N
16
20
24
28
a
0°
8"
0°
8°
0°
8°
0°
8°
QUALITY SEMICONDUCTOR INC.
oju mil ouiV/
n
Plastic Small Outline Gull Wing (SOIC)
24 - 28 Pin (330 mil)
Pln1
RRR RRRRR
H E
ix
D
SO
h x 45°
B
seating plan
planeJ r
Notes :
1 . Refer to applicable symbol list.
2. N is the maximum quantity of lead positions.
3. All dimensions are in inches.
4. Dimensions D and E are to be measured at maximum material condition
but do not include mold flash.Allowable mold flash is 0.006 inch per side.
JEDEC#
MO-059 AA
MO-059 AC
DWG#
PS 24B
PS 28B
Symbol
Min
Max
Min
Max
A
.080
.100
.080
.100
A1
.005
.014
.005
.014
B
.014
.020
.014
.020
C
.006
.010
.006
.010
D
.624
.634
.718
.728
E
.325
.335
.325
.335
e
.044
.056
.044
.056
H
.453
.477
.453
.477
h
.010
.030
.010
.030
L
.020
.050
.020
.050
N
24
28
a
0°
8°
0°
8°
=
8-10
QUALITY SEMICONDUCTOR INC.
S
Package Information
300 Mil SOJ
f
Plastic Small Outline J Bend (SOJ)
20 - 28 Pin (300 mil)
Pin 1
nnnnn
Notes :
1 . Refer to applicable symbol list.
2. N is the maximum quantity of lead positions.
3. All dimensions are in inches.
4. Dimensions D and E are to be measured at maximum material condition
but do not include mold flash.Allowable mold flash is 0.006 inch per side.
JEDEC#
MO-088AD
MO-088 AE
MO-088 AF
DWG#
PJ20A
PJ 24A
PJ 28A
Symbol
Min
Max
Min
Max
Min
Max
A
.120
.140
.120
.140
.120
.140
A1
.025
.045
.025
.045
.025
.045
B
.014
.019
.014
.019
.014
.019
C
.009
.012
.009
.012
.009
.012
D
.502
.512
.602
.612
.701
.711
E
.336
.347
.336
.347
.336
.347
E1
.292
.299
.292
.299
.292
.299
E2
.262
.272
.262
.272
.262
.272
e
.044
.056
.044
.056
.044
.056
h
.010
.016
.010
.016
.010
.016
N
20
24
28
a
QUALITY SEMICONDUCTOR INC.
=
8-11
Package Information
Pin1
Notes: 1 . Refer to applicable symbol list.
2. N is the maximum quantity of lead positions.
3. All dimensions are in inches.
4. Dimensions D and A2 are to be measured at maximum material condition
but do not include mold flash. Allowable mold flash is 0.01 0 inch per side.
JEDEC#
MO-054AA
MO-072AB
MO-072AC
DWG#
PZ16A
PZ20A
PZ24A
Symbol
Min
Max
Min
Max
Min
Max
A
.290
.350
.350
.400
.350
.400
A1
.060
.100
.030
.070
.030
.070
A2
.250
.270
.280
.340
.320
.350
A3
.390
.500
.450
.550
.450
.550
B
.015
.024
.015
.024
.015
.024
C
.008
.012
.008
.012
.008
.012
D
.786
.814
1.008
1.030
1.200
1.250
E
.100
.120
.100
.120
.100
.120
e1
.050 BSC
.050 BSC
.050 BSC
eA
.100
BSC
.100
BSC
.100
BSC
L
, — |
.100
.150
.100
.150
.100
.150
-
M
.035
.085
.035
.085
.035
.085
N
16
20
24
S
.018 | .032
.018
.032
.018 | .032
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